Google TPU:Ironwood 与云厂商自研芯片路线


1. 介绍

1.1. 厂商定位

Google TPU(Tensor Processing Unit)是本组「云厂商自研自用」路线的代表:TPU 为 Google 自研、部署于自有数据中心、通过 Google Cloud 对外服务,不作为独立芯片对外销售。Google 自身是最重要的用户——Gemini、Veo、Imagen 及 Anthropic 的 Claude 均在 TPU 上训练与推理(官方口径)。

本篇叙事主线:云厂商自研自用 + 推理时代(Age of Inference)叙事的提出者。Google 在 2025-04 Ironwood 发布时明确提出「推论时代」概念,把行业重心从训练转向推理侧服务——这一叙事直接对应 Harness 六层中 L1/L2(上下文与工具执行)负载的爆发。

1.2. 基本信息卡

项目内容
公司Google(Alphabet);产品线隶属 Google Cloud
定位云厂商自研 AI 加速器(自用 + 云托管外供,不单卖芯片)
第 7 代 TPUIronwood(2025-04 Google Cloud Next 25 发布;2025 年内正式推出,2025-11 公告 GA 在即)
配套 CPUAxion(Arm 架构自研 CPU,N4A / C4A / C4A metal 实例)
系统框架AI Hypercomputer(计算 + 网络 + 存储 + 软件一体化)
商业模式云实例/承诺用量折扣;无芯片销售;on-prem 未普遍开放
信息截止2026-09-12

1.3. 产品代际

代际发布/GA定位关键规格
v5e2023推理/中小训练197 BF16 TFLOPS、16 GB HBM2e、2D torus、最多 256 卡训练
v5p2023大规模训练459 BF16 TFLOPS、95 GB HBM2e、3D torus、单 Pod 8960 卡、多切片 18432 卡
v6e Trillium2024 末 GA推理/训练918 BF16 TFLOPS、32 GB HBM、较 v5e 能效 +67%、第三代 SparseCore
v7 Ironwood2025 Q4 GA推理优先4614 TFLOPS FP8、192 GB HBM3e、单超 Pod 9216 卡 42.5 ExaFLOPS FP8

CPU 配套:Axion(Arm 架构自研 CPU)与 TPU 组成 Google 自研算力组合;N4A 实例官方称较同级 x86 VM 性价比最高 2 倍(客户实测转述口径:Vimeo 核心转档负载 +30%、ZoomInfo 性价比 +60%)。

1.4. 在 AI Harness 体系中的位置

Google 是唯一一家同时是 Harness 上层玩家(Gemini 模型、ADK 智能体框架,见 02-AI-Agents 组)与底层算力玩家(TPU/Axion)的厂商。TPU 栈对 Harness 六层的独特贡献在于「云托管形态的一体化治理」(L6 完全由 GCP IAM/配额体系承载)与「vLLM 统一 TPU 后端」带来的 L2 开放性。


2. 名词解释

术语英文/缩写释义
TPUTensor Processing UnitGoogle 自研张量处理器,第 7 代为 Ironwood
PodTPU Pod通过 ICI 互连的 TPU 集群,作为单一计算单元调度
Super PodSuper PodIronwood 的 9216 芯片级 Pod 配置
ICIInter-Chip InterconnectGoogle 芯片间高速互联网络;Ironwood 单芯片双向 1.2 Tbps
3D Torus3D TorusTPU Pod 的三维环面互联拓扑
OCSOptical Circuit Switch光路交换,动态重组互联拓扑、绕过故障恢复负载
JupiterJupiterGoogle 数据中心网络技术,串联多个 Super Pod 形成数十万 TPU 集群
SparseCoreSparseCore专用于超大规模 Embedding(排序/推荐)的加速单元,Ironwood 为增强版
PathwaysPathwaysGoogle DeepMind 的 ML 运行时架构,支持跨数千 TPU 的分布式计算
MaxTextMaxTextGoogle 开源 LLM 训练参考实现(JAX/XLA 生态)
XLAAccelerated Linear Algebra线性代数编译器,JAX/PyTorch-XLA 的编译后端
vLLM TPU 后端vLLM on TPUvLLM 推理引擎的 TPU 硬件后端(2025 年官方强化)
GKE Inference GatewayGKE 推理网关,TPU 服务器间智能负载均衡(官方称 TTFT 降低最高 96%)
AxionAxionGoogle 基于 Arm Neoverse 的自研 CPU
多切片Multislice跨 Pod/跨数据中心的数据中心网络扩展训练形态

3. 功能说明与产品线

3.1. TPU 产品代际与规格

见 1.3 节代际表。规格数据以 Google Cloud 官方口径为准(经学舍汇编/telnyx/introl 交叉,A/B 级)。MLPerf 口径(MLCommons,A/B 级):

  1. MLPerf Training 4.1:Trillium 较 v5p 性能/美元最高 1.8 倍;多切片数据中心网络跨域扩展效率 99%(v5p 单 ICI 域 94%);
  2. MLPerf Inference 5.0:Trillium 在 Stable Diffusion XL 吞吐较 v5e 3.5 倍,1000 张图成本 0.22 美元(较 v5e 低 35%)。

3.2. Ironwood:首款推理优先的 TPU

基于 Google 官方博客(2025-04 Next 25 发布文与 2025-11 GA 公告文,A 级)整理:

项目规格/口径
单芯片峰值4614 TFLOPS(FP8)
显存每芯片 192 GB HBM3e(Trillium 的 6 倍);带宽 7.2 TB/s(Trillium 的 4.5 倍)
ICI双向 1.2 Tbps(Trillium 的 1.5 倍);Super Pod 内 9.6 TB/s
配置256 芯片与 9216 芯片两种 Pod 配置
Super Pod 算力42.5 ExaFLOPS FP8(官方称超 24 倍于 El Capitan 超算单 Pod 1.7 ExaFLOPS)
共享 HBMSuper Pod 级高达 1.77 PB
能效较 Trillium 性能功耗比 2 倍;较 2018 年首款 Cloud TPU 近 30 倍
可靠性OCS 光交换动态绕过中断;先进液冷(2020 年起 GW 级部署、99.999% 机队在线率官方口径)
部署初期集中于美国,规划 2026 年中扩展至全球各地区
定位叙事「首款为推理时代设计的 TPU」,官方称 Google 迄今最强、最节能的定制芯片

官方性能对比口径:较 v5p 峰值性能提升 10 倍;较 Trillium 单芯片训练与推理性能提升 4 倍以上。

3.3. Axion CPU 与 AI Hypercomputer

  1. AI Hypercomputer:Google 的整合式超级计算系统(计算 + 网络 + 存储 + 软件协同设计);IDC 报告口径:导入客户平均 353% 三年 ROI、IT 成本降 28%、团队效率提升 55%(转述口径);
  2. Axion 产品组合:N4A(通用 VM 预览版)、C4A、C4A metal(Arm 裸机预览版)——官方定位为 AI 工作流的通用计算骨干(数据准备、检索、应用服务);
  3. GKE Cluster Director:面向 TPU 客户的高级维护、拓扑感知调度与高弹性集群能力。

4. 平台架构

4.1. Pods 互联拓扑

图 6-1|Google TPU Pods 互联拓扑:ICI / OCS / Jupiter 三层

Ironwood Super Pod 互联拓扑(示意) 信息截止 2026-09-12 · 依据 Google 官方博客整理 · 示意:非工程图 Ironwood Super Pod:9216 颗芯片 · 42.5 ExaFLOPS FP8(本图重点) Ironwood ×NIronwood ×NIronwood ×N Ironwood ×NIronwood ×NIronwood ×N Ironwood ×NIronwood ×NIronwood ×N Ironwood ×NIronwood ×N ICI 网络:单芯片双向 1.2 Tbps · Pod 内 9.6 TB/s · 共享 HBM 达 1.77 PB · 3D torus 拓扑 OCS 光路交换 动态重组互联拓扑 · 即时绕过中断恢复负载 服务保持运行,无需整机重启 Jupiter 数据中心网络 串联多个 Super Pod → 数十万 TPU 集群 多切片(Multislice)跨域扩展效率 99%(MLPerf Training 4.1) 软件层:AI Hypercomputer Pathways 运行时 · MaxText(SFT/GRPO)· vLLM TPU 后端 · GKE Cluster Director / Inference Gateway 结构解读:Google 的差异化不在单芯片,而在「光交换 + 数据中心网络 + 软件运行时」的系统级协同。

数据来源:Google 官方博客(2025-04 Ironwood 发布文、2025-11 GA 公告文)、MLCommons MLPerf Training 4.1;拓扑为示意图。

4.2. 软件栈

  1. Pathways:Google DeepMind 的 ML 运行时,跨数千 TPU 的分布式计算编排,客户可借其组合数十万颗 Ironwood;
  2. MaxText:开源 LLM 训练参考实现,新强化 SFT 与 GRPO(生成式强化策略优化)等训练/强化学习技术;
  3. vLLM TPU 后端:官方宣布强化支持,开发者仅需少量配置更改即可在 GPU 与 TPU 之间切换或同时运行;
  4. GKE Inference Gateway:TPU 服务器间智能负载均衡,官方口径 TTFT 降低最高 96%、服务成本降低最高 30%。

5. Harness 设计

5.1. 六层能力总览

支撑产品/机制成熟度
L1 上下文工程SparseCore(第三代)超大 Embedding 加速 / 192 GB 单卡驻留大模型 KV / JAX-XLA 静态图编译中强
L2 工具与执行vLLM 统一 TPU 后端(少量配置切换 GPU/TPU)中强
L3 编排与控制多切片(Multislice)跨数据中心编排 / GKE Cluster Director 拓扑感知调度强(集群编排维度)
L4 记忆与状态Super Pod 1.77 PB 共享 HBM / OCS 动态绕障中强
L5 评估与观测MLPerf 多切片 99% 扩展效率 / GKE Inference Gateway 指标(TTFT/成本)中强
L6 治理与安全云托管形态:GCP IAM/配额体系天然承载;on-prem 未开放强(云治理)/ 弱(私有化不可得)

5.2. L1 上下文工程层

  1. SparseCore:加速超大 Embedding,Ironwood 增强版将能力从 AI 扩展至金融与科学计算(官方口径);
  2. 192 GB 单卡 HBM3e:大模型 KV Cache 单卡驻留,减少跨卡访存;
  3. JAX/XLA 静态图编译:利于大批量推理的算子融合与内存规划——代价是对动态控制流负载(典型智能体工具调用模式)的灵活性弱于 PyTorch eager 路线,选型时需权衡。

5.3. L2 / L3 工具与编排层

vLLM 统一 TPU 后端(第三方称 2—5 倍提升,C 级)显著降低 L2 迁移成本;L3 的差异化在集群编排:多切片(Multislice)机制把训练/推理跨越多个 Pod 甚至多个数据中心组织起来(MLPerf 多切片扩展效率 99%,A 级),GKE Cluster Director 提供拓扑感知调度。MaxText 支持 SFT/GRPO,为后训练与强化学习(智能体能力来源)提供开源参考实现。

5.4. L4 记忆与状态层

Super Pod 级 1.77 PB 共享 HBM 是状态容量的物理上限;OCS 光交换在故障时即时重组拓扑、绕过中断恢复负载,官方口径服务保持运行——这构成云托管形态下 L4 状态连续性的核心机制。

5.5. L5 评估与观测层

MLPerf 多切片 99% 扩展效率可视为集群稳定性与可观测的第三方佐证(A 级);运行时观测依托 GKE Inference Gateway 的 TTFT/成本指标体系。

5.6. L6 治理与安全层

TPU 为云托管形态(无自建集群授权),治理完全依赖 GCP IAM、配额与审计体系——对云原生企业是优势(开箱即得),对私有化需求是硬约束。on-prem TPU 尚未普遍开放;Meta 谈判若落地将成为首个例外(B 级报道口径,见 6.2 节)。


6. 实际案例

6.1. Anthropic:百万颗 TPU 承诺

背景:2025-10/11,Anthropic 宣布获取最高 100 万颗 TPU、2026 年上线超 1 GW 容量,为 Google 历史最大 TPU 承诺(A/B 级);此前已有数十万 Trillium 承诺。

方案:Claude 训推结合 NVIDIA GPU + AWS Trainium + Google TPU 多栈(与 07 篇交叉引用:Anthropic 同时在 Project Rainier 上训练 Claude)。

官方引述:Anthropic 计算主管 James Bradbury 表示 Ironwood 的推理效能与训练可扩展性帮助其高效扩展并满足客户速度与可靠性期望(Ironwood 发布文引述)。

解读:Anthropic 的「多栈硬件中立」策略是本轮算力竞争的标志性事件——头部模型厂商不再单押 NVIDIA,而是按成本与可用性在 GPU / Trainium / TPU 间动态分配。

6.2. 其他客户案例

客户内容可信度
Midjourney从 NVIDIA A100/H100 集群迁移至 TPU v6e Pod,月推理开销从约 210 万美元降至 70 万美元以下(约 65% 降幅);同时公开反思 TPU 路线拖慢研究迭代速度(迁移成本与灵活性代价)——两口径并列:省钱 vs 研发敏捷性受损C 级(多来源交叉,原始信源为社区/访谈口径)
Character.AI2025 年迁移,公开口径 3.8 倍成本改善C 级
Waymark视频生成 4 倍降本C 级(第三方汇编)
Perplexity / Stability AI / Hugging Face全推理栈上 TPU v5e/v6;40% 图像推理迁至 v6;>7B 模型默认提供 TPU 端点C 级(第三方汇编)
Lightricks / Essential AIIronwood 早期用户(官方发布文引述)A 级(官方引述)
Google 自用Gemini 系列在 TPU Pods 训练A 级
Meta(谈判中)2025-10 报道:与 Google 就数十亿美元 TPU 部署深入谈判(2026 年中起,2027 年可能 on-prem);Zuckerberg Q3 2025 财报电话会确认「探索多家硅片供应商」B 级(The Information/Reuters 转述;截至 2026-09 未官宣)

6.3. 成本口径冲突并列

TPU 的成本优势存在相互冲突的口径,按纪律并列、不择一:

口径内容来源与可信度
第三方 TCO 模型3 年 TCO 模型显示 TPU 集群较 H100 集群低约 56%;8 卡 v5e 跑 Llama2-70B 约 2175 tokens/s、11 美元/小时;Trillium 承诺用量折扣可低至 0.39 美元/卡时introl / baud.rs 第三方分析(C/D 级,模型推算非实测)
Midjourney 实践反思推理成本确实大幅下降(约 65%),但公开反思 TPU 路线拖慢研究迭代速度(迁移成本与灵活性代价)C 级(社区/访谈口径)
IDC 转述AI Hypercomputer 客户平均 353% 三年 ROI厂商委托研究转述(B 级)

结论:TPU 的成本优势在稳定、大批量、XLA 兼容的推理负载上证据较强;在研究敏捷性与动态负载上存在明确的反例证言。引用任何单一数字前必须核对其负载假设。


7. 总结

优势

  1. 系统级协同设计:OCS + Jupiter + Pathways 构成的集群编排能力(L3)为本组最强;
  2. 推理时代叙事与产品对齐:Ironwood 是首款推理优先的 TPU,SparseCore/共享 HBM/GKE Inference Gateway 全部指向推理负载;
  3. 成本证据链:MLPerf 性能/美元口径(Trillium 1.8 倍 v5p)与多个客户降本案例互相印证。

劣势

  1. 云锁定:无法私有化部署(on-prem 未开放),XLA/JAX 生态对动态控制流负载不够友好;
  2. 价格不透明:无公开标价,仅承诺用量折扣区间;
  3. Meta 级 on-prem 交易未官宣,路线存在不确定性。

适用边界:已在 GCP 生态、负载以稳定批量推理为主的团队;XLA/JAX 技术栈团队;多栈策略下的 NVIDIA 替代/补充算力。不适合强私有化要求与重度动态控制流研究负载。

选型建议:以承诺用量折扣谈判获取价格区间;先在 v6e 上验证目标模型的 XLA 兼容性再评估 Ironwood 迁移;把「研究迭代速度」作为与成本并列的一级决策变量(Midjourney 反例)。

信息缺口声明

  1. Ironwood / Trillium 官方价格表缺失(Google 不公开标价,仅有承诺用量折扣区间转述);
  2. Axion 与 TPU 协同的官方架构文档散落于多篇博客,缺统一白皮书;
  3. Meta—Google TPU 交易截至 2026-09 未获官宣,只能以「谈判/报道」表述;
  4. 单芯片 HBM 带宽存在 7.2 TB/s(官方博客)与 7.37 TB/s(第三方汇编)两个数字,本文以官方博客口径 7.2 TB/s 为准。

8. 参考资料

  1. Ironwood: 首款适用于 AI 推论时代的 Google TPU — Google 官方博客(Amin Vahdat),2025-04-09。https://blog.google/intl/zh-tw/products/cloud/ironwood-the-first-google-tpu-for-the-age-of-inference/
  2. Ironwood TPU 与全新 Axion 虚拟机(GA 公告)— Google Cloud Blog,2025-11。https://cloud.google.com/blog/products/compute/ironwood-tpus-and-new-axion-based-vms-for-your-ai-workloads
  3. The Diversification of AI Hardware: Beyond NVIDIA's Dominance — Ecitis(含 TPU 各代规格与 MLPerf 数据汇编),2025。https://blog.ecitis.org/ai-hardware-landscape
  4. Google TPU vs NVIDIA GPU: An Infrastructure Decision Framework — Introl,2025。https://introl.com/blog/google-tpu-vs-nvidia-gpu-infrastructure-decision-framework-2025
  5. TPU vs GPU Compared for AI Training and Inference — Telnyx Learn,2025。https://telnyx.com/learn-ai/tpu-vs-gpu
  6. Cloud TPU 官方文档 — Google Cloud,2025。https://cloud.google.com/tpu/docs
  7. AWS activates Project Rainier cluster of nearly 500,000 Trainium2 chips(含 Anthropic TPU 百万颗扩约交叉报道)— Data Center Dynamics,2025-11。https://www.datacenterdynamics.com/en/news/aws-activates-project-rainier-cluster-of-nearly-500000-trainium2-chips/
  8. MLPerf Benchmarks 结果库 — MLCommons,2025。https://mlcommons.org/benchmarks/inference/
  9. Nvidia to Google TPU Migration 2025(TCO 模型,D 级分析推算)— TinyComputers/baud.rs,2025。https://baud.rs/4aoJ1v
  10. 谷歌云发布最强自研 TPU:十年研发结晶,性能四倍于前代 — 财联社,2025-11-06。https://www.cls.cn/detail/2193551

Google TPU: Ironwood and Cloud Providers' In-House Chip Roadmap

1. Introduction

1.1. Vendor Positioning

Google TPU (Tensor Processing Unit) is the representative of this group's "in-house development and use by cloud providers" roadmap: the TPU is developed by Google, deployed in its own data centers, and offered externally through Google Cloud as a service — it is not sold as a standalone chip. Google itself is the most important user — Gemini, Veo, Imagen, and Anthropic's Claude are all trained and inferred on TPUs (official statement).

The narrative thread of this article: a cloud provider's in-house development and use, and the originator of the "Age of Inference" narrative. When Google released Ironwood in 2025-04, it explicitly proposed the concept of the "Age of Inference," shifting the industry's focus from training to inference-side services — this narrative directly corresponds to the explosion of L1/L2 (context and tool execution) workloads in Harness's six layers.

1.2. Basic Information Card

ItemContent
CompanyGoogle (Alphabet); the product line belongs to Google Cloud
PositioningCloud provider's in-house AI accelerator (in-house use + cloud-hosted external offering; chips not sold separately)
7th-gen TPUIronwood (announced at 2025-04 Google Cloud Next 25; formally rolled out during 2025, with 2025-11 announcement that GA was imminent)
Companion CPUAxion (Arm-architecture in-house CPU, N4A / C4A / C4A metal instances)
System frameworkAI Hypercomputer (integrated compute + network + storage + software)
Business modelCloud instances / committed-use discounts; no chip sales; on-prem not broadly available
Information cutoff2026-09-12

1.3. Product Generations

GenerationRelease/GAPositioningKey Specs
v5e2023Inference / mid-small training197 BF16 TFLOPS, 16 GB HBM2e, 2D torus, up to 256-chip training
v5p2023Large-scale training459 BF16 TFLOPS, 95 GB HBM2e, 3D torus, 8960 chips per Pod, 18432 chips with multislice
v6e TrilliumGA end of 2024Inference / training918 BF16 TFLOPS, 32 GB HBM, +67% energy efficiency over v5e, 3rd-gen SparseCore
v7 Ironwood2025 Q4 GAInference-first4614 TFLOPS FP8, 192 GB HBM3e, 9216 chips per Super Pod / 42.5 ExaFLOPS FP8

CPU companion: Axion (Arm-architecture in-house CPU) forms Google's in-house compute combination with the TPU; the N4A instance is officially claimed to offer up to 2x better price/performance than comparable x86 VMs (as relayed from customer measurements: Vimeo core transcoding workloads +30%, ZoomInfo price/performance +60%).

1.4. Position in the AI Harness System

Google is the only vendor that is simultaneously a top-layer player in Harness (Gemini models, ADK agent framework, see the 02-AI-Agents group) and a bottom-layer compute player (TPU/Axion). The TPU stack's unique contribution to Harness's six layers lies in "integrated governance in a cloud-hosted form" (L6 fully carried by the GCP IAM/quota system) and the L2 openness brought by the "vLLM unified TPU backend."


2. Glossary

TermEnglish/AbbreviationDefinition
TPUTensor Processing UnitGoogle's in-house tensor processor; the 7th generation is Ironwood
PodTPU PodA TPU cluster interconnected via ICI, scheduled as a single compute unit
Super PodSuper PodIronwood's 9216-chip Pod configuration
ICIInter-Chip InterconnectGoogle's high-speed inter-chip interconnect network; Ironwood single-chip bidirectional 1.2 Tbps
3D Torus3D TorusThe three-dimensional torus interconnect topology of a TPU Pod
OCSOptical Circuit SwitchOptical circuit switching; dynamically reorganizes the interconnect topology to route around failures and restore workloads
JupiterJupiterGoogle data center network technology that links multiple Super Pods to form clusters of hundreds of thousands of TPUs
SparseCoreSparseCoreAcceleration unit dedicated to ultra-large-scale Embedding (ranking/recommendation); enhanced version in Ironwood
PathwaysPathwaysGoogle DeepMind's ML runtime architecture supporting distributed compute across thousands of TPUs
MaxTextMaxTextGoogle's open-source LLM training reference implementation (JAX/XLA ecosystem)
XLAAccelerated Linear AlgebraLinear algebra compiler; compile backend of JAX/PyTorch-XLA
vLLM TPU backendvLLM on TPUTPU hardware backend for the vLLM inference engine (officially strengthened in 2025)
GKE Inference GatewayGKE inference gateway; intelligent load balancing among TPU servers (officially up to 96% TTFT reduction)
AxionAxionGoogle's in-house CPU based on Arm Neoverse
MultisliceMultisliceTraining form extended across Pods/data centers via data center networking

3. Functionality and Product Line

3.1. TPU Product Generations and Specs

See the generation table in Section 1.3. Spec data follows the Google Cloud official figures (cross-checked via xueshe compilation / telnyx / introl, A/B grade). MLPerf figures (MLCommons, A/B grade):

  1. MLPerf Training 4.1: Trillium offers up to 1.8x the performance/dollar of v5p; multislice data center network cross-domain scaling efficiency of 99% (94% in a single ICI domain for v5p);
  2. MLPerf Inference 5.0: Trillium's Stable Diffusion XL throughput is 3.5x that of v5e, at a cost of $0.22 per 1000 images (35% lower than v5e).

3.2. Ironwood: The First Inference-First TPU

Compiled based on Google's official blogs (the 2025-04 Next 25 announcement post and the 2025-11 GA announcement post, A grade):

ItemSpec / Figure
Single-chip peak4614 TFLOPS (FP8)
Memory192 GB HBM3e per chip (6x Trillium); bandwidth 7.2 TB/s (4.5x Trillium)
ICIBidirectional 1.2 Tbps (1.5x Trillium); 9.6 TB/s within a Super Pod
ConfigurationsTwo Pod configurations: 256 chips and 9216 chips
Super Pod compute42.5 ExaFLOPS FP8 (officially over 24x the single-Pod 1.7 ExaFLOPS of the El Capitan supercomputer)
Shared HBMUp to 1.77 PB at the Super Pod level
Energy efficiency2x the performance-per-watt of Trillium; nearly 30x the first Cloud TPU of 2018
ReliabilityOCS optical switching to dynamically route around interruptions; advanced liquid cooling (GW-scale deployments since 2020, 99.999% fleet online rate by official figures)
DeploymentInitially concentrated in the US, planned to expand to regions worldwide by mid-2026
Positioning narrative"The first TPU designed for the Age of Inference"; officially Google's most powerful and most energy-efficient custom chip to date

Official performance comparison figures: 10x higher peak performance than v5p; over 4x higher single-chip training and inference performance than Trillium.

3.3. Axion CPU and AI Hypercomputer

  1. AI Hypercomputer: Google's integrated supercomputing system (co-designed compute + network + storage + software); per the IDC report: average 353% three-year ROI for adopting customers, 28% IT cost reduction, 55% team efficiency gain (relayed figures);
  2. Axion product portfolio: N4A (general-purpose VM preview), C4A, C4A metal (Arm bare-metal preview) — officially positioned as the general-purpose compute backbone for AI workloads (data preparation, retrieval, application serving);
  3. GKE Cluster Director: advanced maintenance, topology-aware scheduling, and high-resilience cluster capabilities for TPU customers.

4. Platform Architecture

4.1. Pods Interconnect Topology

Figure 6-1 | Google TPU Pods Interconnect Topology: The Three Layers of ICI / OCS / Jupiter

Ironwood Super Pod 互联拓扑(示意) 信息截止 2026-09-12 · 依据 Google 官方博客整理 · 示意:非工程图 Ironwood Super Pod:9216 颗芯片 · 42.5 ExaFLOPS FP8(本图重点) Ironwood ×NIronwood ×NIronwood ×N Ironwood ×NIronwood ×NIronwood ×N Ironwood ×NIronwood ×NIronwood ×N Ironwood ×NIronwood ×N ICI 网络:单芯片双向 1.2 Tbps · Pod 内 9.6 TB/s · 共享 HBM 达 1.77 PB · 3D torus 拓扑 OCS 光路交换 动态重组互联拓扑 · 即时绕过中断恢复负载 服务保持运行,无需整机重启 Jupiter 数据中心网络 串联多个 Super Pod → 数十万 TPU 集群 多切片(Multislice)跨域扩展效率 99%(MLPerf Training 4.1) 软件层:AI Hypercomputer Pathways 运行时 · MaxText(SFT/GRPO)· vLLM TPU 后端 · GKE Cluster Director / Inference Gateway 结构解读:Google 的差异化不在单芯片,而在「光交换 + 数据中心网络 + 软件运行时」的系统级协同。

Data sources: Google's official blogs (2025-04 Ironwood announcement post, 2025-11 GA announcement post), MLCommons MLPerf Training 4.1; the topology is a schematic illustration.

4.2. Software Stack

  1. Pathways: Google DeepMind's ML runtime; distributed-compute orchestration across thousands of TPUs, which customers can use to combine hundreds of thousands of Ironwood chips;
  2. MaxText: open-source LLM training reference implementation, newly strengthening training/reinforcement-learning techniques such as SFT and GRPO (generative reinforcement policy optimization);
  3. vLLM TPU backend: officially announced strengthened support — developers need only minor configuration changes to switch between or run concurrently on GPUs and TPUs;
  4. GKE Inference Gateway: intelligent load balancing among TPU servers; by official figures, up to 96% TTFT reduction and up to 30% service cost reduction.

5. Harness Design

5.1. Overview of Six-Layer Capabilities

LayerSupporting Product / MechanismMaturity
L1 Context engineeringSparseCore (3rd-gen) ultra-large Embedding acceleration / 192 GB per-card residency for large-model KV / JAX-XLA static-graph compilationMedium-strong
L2 Tools & executionvLLM unified TPU backend (switch GPU/TPU with minor configuration)Medium-strong
L3 Orchestration & controlMultislice cross-data-center orchestration / GKE Cluster Director topology-aware schedulingStrong (at the cluster-orchestration dimension)
L4 Memory & stateSuper Pod 1.77 PB shared HBM / OCS dynamic fault bypassMedium-strong
L5 Evaluation & observabilityMLPerf multislice 99% scaling efficiency / GKE Inference Gateway metrics (TTFT/cost)Medium-strong
L6 Governance & securityCloud-hosted form: natively carried by GCP IAM/quota system; on-prem not availableStrong (cloud governance) / Weak (private deployment unavailable)

5.2. L1 Context Engineering Layer

  1. SparseCore: accelerates ultra-large Embedding; the Ironwood enhanced version extends the capability from AI to finance and scientific computing (official statement);
  2. 192 GB per-card HBM3e: large-model KV Cache resident on a single card, reducing cross-card memory access;
  3. JAX/XLA static-graph compilation: favorable for operator fusion and memory planning in large-batch inference — at the cost of lower flexibility than the PyTorch eager path for dynamic-control-flow workloads (a typical agent tool-calling pattern), so selection requires trade-offs.

5.3. L2 / L3 Tools & Orchestration Layer

The vLLM unified TPU backend (third parties cite a 2–5x improvement, C grade) significantly lowers L2 migration costs; L3's differentiation lies in cluster orchestration: the Multislice mechanism organizes training/inference across multiple Pods and even multiple data centers (MLPerf multislice scaling efficiency of 99%, A grade), and GKE Cluster Director provides topology-aware scheduling. MaxText supports SFT/GRPO, offering an open-source reference implementation for post-training and reinforcement learning (a source of agent capabilities).

5.4. L4 Memory & State Layer

The 1.77 PB shared HBM at the Super Pod level is the physical ceiling of state capacity; OCS optical switching instantly reorganizes the topology on failure, routing around interruptions to restore workloads — by official figures the service keeps running — which constitutes the core mechanism of L4 state continuity in the cloud-hosted form.

5.5. L5 Evaluation & Observability Layer

MLPerf's 99% multislice scaling efficiency can be regarded as third-party evidence of cluster stability and observability (A grade); runtime observability relies on GKE Inference Gateway's TTFT/cost metric system.

5.6. L6 Governance & Security Layer

The TPU is a cloud-hosted form (no authorization to build private clusters), so governance depends entirely on the GCP IAM, quota, and audit systems — an advantage for cloud-native enterprises (ready out of the box), but a hard constraint for private-deployment needs. On-prem TPUs are not yet broadly available; if the Meta negotiations materialize, they would become the first exception (B-grade reporting figure, see Section 6.2).


6. Case Studies

6.1. Anthropic: The One-Million-TPU Commitment

Background: In 2025-10/11, Anthropic announced access to up to 1 million TPUs with over 1 GW of capacity coming online in 2026, the largest TPU commitment in Google's history (A/B grade); previously there had been commitments of hundreds of thousands of Trillium chips.

Approach: Claude trains and infers across a multi-stack of NVIDIA GPUs + AWS Trainium + Google TPUs (cross-referenced with article 07: Anthropic is simultaneously training Claude on Project Rainier).

Official quote: Anthropic's head of compute James Bradbury said Ironwood's inference performance and training scalability help it scale efficiently and meet customer expectations for speed and reliability (quoted from the Ironwood announcement post).

Interpretation: Anthropic's "hardware-neutral multi-stack" strategy is a landmark event in this round of compute competition — leading model vendors are no longer betting solely on NVIDIA, but dynamically allocating across GPU / Trainium / TPU based on cost and availability.

6.2. Other Customer Cases

CustomerContentCredibility
MidjourneyMigrated from NVIDIA A100/H100 clusters to a TPU v6e Pod, cutting monthly inference cost from about $2.1M to under $0.7M (~65% reduction); at the same time publicly reflected that the TPU route slowed research iteration speed (migration cost and flexibility trade-off) — two figures presented in parallel: cost savings vs. impaired R&D agilityC grade (cross-checked across multiple sources; original sources are community/interview figures)
Character.AIMigrated in 2025, publicly citing 3.8x cost improvementC grade
Waymark4x cost reduction for video generationC grade (third-party compilation)
Perplexity / Stability AI / Hugging FaceEntire inference stack on TPU v5e/v6; 40% of image inference moved to v6; TPU endpoints provided by default for >7B modelsC grade (third-party compilation)
Lightricks / Essential AIEarly Ironwood users (quoted in the official announcement post)A grade (official quote)
Google internal useGemini family trained on TPU PodsA grade
Meta (in negotiation)2025-10 reports: in deep negotiation with Google over a multi-billion-dollar TPU deployment (starting mid-2026, possibly on-prem in 2027); Zuckerberg confirmed "exploring multiple silicon suppliers" on the Q3 2025 earnings callB grade (relayed via The Information/Reuters; not officially announced as of 2026-09)

6.3. Conflicting Cost Figures Presented in Parallel

Alternating, conflicting figures exist regarding the TPU's cost advantage; per discipline, they are presented in parallel rather than picking one:

FigureContentSource & Credibility
Third-party TCO modelA 3-year TCO model shows TPU clusters are about 56% cheaper than H100 clusters; an 8-card v5e running Llama2-70B yields about 2175 tokens/s at $11/hour; Trillium committed-use discounts can go as low as $0.39/card-hourintrol / baud.rs third-party analysis (C/D grade, model-based projections, not measurements)
Midjourney practice reflectionInference cost did drop substantially (~65%), but it publicly reflected that the TPU route slowed research iteration speed (migration cost and flexibility trade-off)C grade (community/interview figures)
IDC relayedAI Hypercomputer customers average 353% three-year ROIVendor-commissioned research relay (B grade)

Conclusion: the TPU's cost advantage shows stronger evidence on stable, large-batch, XLA-compatible inference workloads; there is clear countervailing testimony on research agility and dynamic workloads. Before citing any single number, you must verify its workload assumptions.


7. Summary

Advantages:

  1. System-level co-design: the cluster-orchestration capability (L3) built from OCS + Jupiter + Pathways is the strongest in this group;
  2. Alignment of the Age-of-Inference narrative with products: Ironwood is the first inference-first TPU, and SparseCore/shared HBM/GKE Inference Gateway all point to inference workloads;
  3. Cost evidence chain: MLPerf performance/dollar figures (Trillium 1.8x v5p) corroborate multiple customer cost-reduction cases.

Disadvantages:

  1. Cloud lock-in: cannot be deployed privately (on-prem not available), and the XLA/JAX ecosystem is not friendly to dynamic-control-flow workloads;
  2. Opaque pricing: no public list price, only a range of committed-use discounts;
  3. Meta-level on-prem deals unannounced, leaving the roadmap with uncertainty.

Applicability boundary: teams already in the GCP ecosystem whose workloads are dominated by stable batch inference; XLA/JAX tech-stack teams; NVIDIA replacement/supplementary compute under a multi-stack strategy. Not suitable for strong private-deployment requirements or heavy dynamic-control-flow research workloads.

Selection recommendation: negotiate for a price range with committed-use discounts; first validate the target model's XLA compatibility on v6e before evaluating an Ironwood migration; treat "research iteration speed" as a first-class decision variable on par with cost (the Midjourney counterexample).

Information Gap Statement

  1. No official price list for Ironwood / Trillium (Google does not publish list prices, only relayed committed-use discount ranges);
  2. Official architecture documentation for Axion–TPU synergy is scattered across multiple blog posts, lacking a unified white paper;
  3. The Meta–Google TPU deal has not been officially announced as of 2026-09 and can only be described as "negotiation/reporting";
  4. Two figures exist for single-chip HBM bandwidth — 7.2 TB/s (official blog) and 7.37 TB/s (third-party compilation); this article follows the official blog figure of 7.2 TB/s.

8. References

  1. Ironwood: The First Google TPU for the Age of Inference — Google official blog (Amin Vahdat), 2025-04-09. https://blog.google/intl/zh-tw/products/cloud/ironwood-the-first-google-tpu-for-the-age-of-inference/
  2. Ironwood TPUs and New Axion-Based VMs (GA announcement) — Google Cloud Blog, 2025-11. https://cloud.google.com/blog/products/compute/ironwood-tpus-and-new-axion-based-vms-for-your-ai-workloads
  3. The Diversification of AI Hardware: Beyond NVIDIA's Dominance — Ecitis (contains TPU generation specs and MLPerf data compilation), 2025. https://blog.ecitis.org/ai-hardware-landscape
  4. Google TPU vs NVIDIA GPU: An Infrastructure Decision Framework — Introl, 2025. https://introl.com/blog/google-tpu-vs-nvidia-gpu-infrastructure-decision-framework-2025
  5. TPU vs GPU Compared for AI Training and Inference — Telnyx Learn, 2025. https://telnyx.com/learn-ai/tpu-vs-gpu
  6. Cloud TPU official documentation — Google Cloud, 2025. https://cloud.google.com/tpu/docs
  7. AWS activates Project Rainier cluster of nearly 500,000 Trainium2 chips (includes cross-reporting on Anthropic's million-TPU expansion) — Data Center Dynamics, 2025-11. https://www.datacenterdynamics.com/en/news/aws-activates-project-rainier-cluster-of-nearly-500000-trainium2-chips/
  8. MLPerf Benchmarks results library — MLCommons, 2025. https://mlcommons.org/benchmarks/inference/
  9. Nvidia to Google TPU Migration 2025 (TCO model, D-grade analytical projection) — TinyComputers/baud.rs, 2025. https://baud.rs/4aoJ1v
  10. Google Cloud releases its most powerful in-house TPU: a decade of R&D, 4x the performance of its predecessor — Cailianshe (财联社), 2025-11-06. https://www.cls.cn/detail/2193551