AI Chips

1. Introduction

1.1. Background

AI chips (GPU/NPU accelerators) are the bottom layer of the entire AI Infra series: every supernode form factor, cluster scale, and framework strategy is built on a single chip's compute, memory, and interconnect capabilities. In 2025–2026 two main threads unfolded in this field in parallel: the overseas route, represented by NVIDIA, accelerates iteration generation by generation (Blackwell → Rubin → Rubin Ultra), while the domestic route, represented by Huawei Ascend, advances with "one generation per year" (950PR/950DT → 960 → 970), supplemented by self-developed HBM and self-developed data formats to fill ecosystem gaps.

Unlike the design-side perspective (how chips are designed and manufactured; see 02-行业赋能/04-硬件研发组/01-chip-design.md etc.), this article focuses on the runtime side: with what parameters a chip participates in a cluster, by what baseline it is measured, and with what structure it influences selection. All parameter citations follow a unified rule: state the source level (A级 official / B级 authoritative relay / C级 to be verified), and present conflicting baselines side by side.

1.2. Definition and Scope

The AI chip direction covers the following on the runtime side:

Boundary note: chip internal design (architecture verification, packaging, testing) is outside this direction; see 04-硬件研发组 for details; whole-machine form factors (servers, supernodes) are covered in this group's 02-supernode.md.

1.3. Position in the AI Harness System

In the Harness six-layer capability model, the chip is the physical foundation of the L2 execution layer; its effect on other layers is transmitted through physical parameters:

Bottleneck-layer judgment: this direction's own bottleneck lies not in L3 but in the physical ceiling of L1 — when context engineering demands longer effective context and larger KV Cache, what hits the ceiling first is single-card HBM capacity and bandwidth. Therefore, among chip roadmap parameters, memory parameters (capacity, bandwidth, stack layers) deserve more sustained tracking than peak compute.

1.4. Current State: Two Roadmaps and One Landscape

1.4.1. Overseas Roadmap: Blackwell → Rubin → Rubin Ultra

• Rubin GPU (inside Vera Rubin NVL72, delivered 2026 H2): TSMC 3nm, ~336 billion transistors, 288 GB HBM4, 22 TB/s memory bandwidth; NVLink 6 single GPU 3.6 TB/s (Level A, NVIDIA product page, marked "Preliminary information", i.e. preliminary specifications).
• Rubin Ultra NVL576: planned 2027 H2, 576 GPUs in a single NVLink domain (Level A, teaser baseline).
• New form factor: NVIDIA Groq 3 LPX rack (officially announced at GTC 2026-03): 256 LPUs, 128 GB SRAM, 40 PB/s memory bandwidth, 640 TB/s scale-up, co-designed with NVL72, claiming a 35× per-watt inference improvement for trillion-parameter models (Level A announcement fact; the performance multiple is the vendor's claim).

1.4.2. Domestic Roadmap: Ascend One Generation per Year (official at HC2025, Level A)

Companion software and formats (announced at the same event, Level A): newly added FP8/MXFP8/MXFP4 and self-developed HiF8/HiF4 data formats (Huawei states HiF8 accuracy is close to FP16); new SIMD/SIMT homomorphism; memory access granularity reduced from 512B to 128B; CANN compiler and virtual instruction set interfaces opened; Mind series suites and openPangu open-sourced (completed by 2025-12-31).

1.4.3. Market Landscape and Interconnect Standard Participation

Market landscape (IDC baseline, relayed through media, Level B/C; see 04-硬件研发组 05-ai-infra.md for the full record): 2025 total China AI accelerator card shipments were about 4 million units, domestic vendors about 1.65 million (41%), Huawei Ascend 812,000 (20.3%, first domestically), NVIDIA about 2.2 million (about 55%). This article only gives a landscape overview and does not repeat R03's full data.

Interconnect standard participation (expanded in 03-cluster.md): NVIDIA builds its own system with NVLink (closed) + NVLink Fusion (semi-open access); the UALink consortium released the 1.0 spec in 2025-04 (up to 1024 accelerators per Pod, 200 GT/s per channel, memory-semantic access), and in 2026-04 released 2.0 and companion specs and added In-Network Compute; on the domestic side, Xinlian Technology (芯动科技) released a full suite of UALink IP in 2026-05 (112G in production, 224G taped out — Level C, each entry needs its source marked).

Figure 1-1 | 2025 China AI accelerator card shipment landscape and dual-roadmap comparison

Data sources: the shipment landscape is IDC data relayed through media (Level B/C; see 04-硬件研发组 05-ai-infra.md); the roadmaps are from Huawei HC2025 and NVIDIA product pages (Level A). The "other domestic vendors" figure is derived by subtracting NVIDIA and Ascend from the total.

2. Glossary

3. Case Studies

3.1. Ascend 910C Runtime Measurement: The Chip Foundation of CloudMatrix 384

Evidence level: A (official paper by Huawei and SiliconFlow, arXiv 2506.12708)

3.1.1. Background

Under process constraints, when single-chip parameters lag, whether the cluster route holds depends on a single chip's real runtime parameters and its composability. This paper disclosed for the first time first-hand runtime parameters of the Ascend 910C in the CloudMatrix 384 supernode, making it the most important anchor data on the runtime side of domestic chips.

3.1.2. Approach

• Packaging and compute: dual-die packaging, ~376 TFLOPS dense BF16 per die, ~752 TFLOPS packaged in total.
• Memory: package integrates 8 memory stacks (16 GB each), 128 GB total (64 GB per die).
• On-chip interconnect: unidirectional UB bandwidth of 392 GB/s per die.
• Node form factor: 8 NPUs + 4 Kunpeng CPUs + 7 on-board UB switch chips per node; an additional 400 Gbps RDMA unidirectional link per NPU, 3.2 Tbps total per node.
• System composition: 384 Ascend 910Cs + 192 Kunpeng CPUs interconnected via the UB network into a supernode (supernode details in 02-supernode.md Case 1).

3.1.3. Results

• This chip combination lets CloudMatrix-Infer on CM384 achieve Prefill 6688 tokens/s/NPU and Decode 1943 tokens/s/NPU on DeepSeek-R1 (INT8 quantization; accuracy on 16 benchmarks comparable to DeepSeek's official API) — showing that insufficient single-chip parameters can be partly compensated by system-level interconnect and quantization strategies (inference details in 05-inference-framework.md Case 1).
• Significance of the paper: the industry's first disclosure of full-stack details for ten-thousand-GPU-scale MoE serving outside the NVIDIA ecosystem, providing reproducible evidence for the domestic "system compensates for single points" route.

Harness interpretation: the 910C's 128 GB packaged memory and UB interconnect determine the feasible region of L1 context engineering in this ecosystem (KV Cache sharing across cards relies on unified addressing); its INT8 route (no FP8 support) directly limits the range of the performance–accuracy tradeoff in L5 evaluation.

3.2. Ascend One-Generation-Per-Year Roadmap: 950PR/950DT to 970

Evidence level: A (official announcement at Huawei Connect 2025)

3.2.1. Background

At HC2025, Huawei clearly judged that "China's semiconductor manufacturing process will lag for a long time, and sustainable compute can only be based on actually obtainable process nodes" (Level A). Under this constraint, its roadmap strategy shifted from "chasing single-point process" to "one generation per year + self-developed companions": self-developed HBM to fill storage, self-developed data formats to fill precision, and opening CANN and the virtual instruction set to fill the ecosystem.

3.2.2. Approach

The four generations of chips listed in the Section 1.4.2 roadmap table (950PR/950DT/960/970), combined with three systematic strategies:

• Self-developed HBM series: HiBL 1.0 (low-cost, carried by the 950PR) and HiZQ 2.0 (carried by the 950DT, 144 GB / 4 TB/s), reducing dependence on third-party HBM.
• Self-developed data formats: HiF8/HiF4 coexist with MXFP8/MXFP4, adding domestic options to the precision–performance tradeoff; meanwhile memory access granularity drops from 512B to 128B, improving fine-grained memory access efficiency.
• Ecosystem openness: the CANN compiler and virtual instruction set interfaces are opened, and the Mind series suites and openPangu are open-sourced (completed by 2025-12-31), treating the cost of migrating "onto Ascend" as a first-class problem.

3.2.3. Results

• Interconnect bandwidth jumps a generation: 950DT's 2 TB/s is 2.5× over the 910C, directly determining the scale of the Scale-up domain it can join (paired with the Atlas 950 SuperPoD's 8192-card network, see 02-supernode.md Case 2).
• Roadmap predictability itself is an effect: at a cadence of one tier per year from 2026 Q1 to 2028 Q4, it gives downstream cluster planning (03-cluster.md) a time baseline for procurement and capacity decisions.
• This case's effect data are all published baselines; measured MFU/ETTR-type metrics had not been independently validated as of the information cutoff, so the "official release" qualifier should be retained when citing.

3.3. NVIDIA Rubin: The Chip Generation of Vera Rubin NVL72

Evidence level: A (NVIDIA product page and GTC 2026 press release, marked "preliminary specifications")

3.3.1. Background

After Blackwell, NVIDIA continues the "one generation per year" cadence with Rubin: full production announced at CES 2026-01, all seven chips fully mass-produced announced at GTC 2026, delivery in 2026 H2; Microsoft Azure completed the first validation on 2026-03-14.

3.3.2. Approach

• Rubin GPU: TSMC 3nm, ~336 billion transistors (encyclopedia baseline, A/B cross-checked), 288 GB HBM4, 22 TB/s memory bandwidth.
• Interconnect: NVLink 6 single GPU 3.6 TB/s all-to-all; rack NVLink Switch total bandwidth 260 TB/s (supernode view in 02-supernode.md Case 3).
• Whole machine: NVL72 totaling NVFP4 inference 3600 PFLOPS (sparse) / training 2520 PFLOPS (dense), FP16/BF16 288 PFLOPS, HBM4 total capacity 20.7 TB, LPDDR5X 54 TB.

3.3.3. Results

• Generation comparison (MLPerf cross-baseline, Level B/C relay): in MLPerf Training v5.0, GB200 per-GPU training throughput reaches up to 2.6× an equivalent Hopper; in MLPerf Inference v5.0, per-GPU inference throughput is about 3.4×. Public benchmark results of Rubin versus Blackwell had not been seen as of the information cutoff and are marked as a gap.
• Conflicting baselines shown side by side (must be retained): NVL72's total HBM4 bandwidth appears as two baselines, 1,400 TB/s and 1,580 TB/s, on different NVIDIA pages. This article follows the research report's recommendation to cite 1,580 TB/s while noting that the other baseline exists, and marks both as [To be verified].
• Rubin Ultra NVL576 planned 2027 H2 (teaser baseline, Level A, non-committal delivery).

4. Practice Standards

Nature statement: the AGENTS.md and SKILL.md below are draft proposals distilled from public industry practice, not the text of official industry standards. No public standard exemplar for the AI chip direction was found. The group-level governing spec is in the same directory's AGENTS.md; the following is a trimmed version for the chip direction.

4.1. AGENTS.md Specification

4.1.1. AGENTS.md (AI Chip Direction)

# AGENTS.md —— AI Infra 组 · AI 芯片方向

> 本文为基于行业实践提炼的建议稿，非官方行业标准原文。
> 上位规范：01-AI-Infra组/AGENTS.md（生产集群不可逆动作禁止清单、变更窗口、可观测要求）。

## 角色与边界
- 角色：AI 芯片运行侧智能体，负责芯片选型比对、参数口径核验、
  显存与互联预算测算、数据格式适配评估。
- 不负责：芯片设计/验证/封装/测试问题（转交 04-硬件研发组）、采购决策、
  出口管制合规结论（仅转述公开政策，不下判断）。
- 所有芯片参数必须标来源级别（A 官方 / B 权威转述 / C 待核实）与口径性质
  （实测 / 发布口径 / 初步规格）。

## 环境假设
执行前必须显式声明：
- 目标芯片型号、代际、封装形态（单 die / 双 die）、显存容量与带宽。
- 互联体系：所属 Scale-up 域（NVLink / UB / UALink / 其他）及带宽。
- 数据格式支持集：FP8 / MXFP8 / MXFP4 / NVFP4 / HiF8 / HiF4 等。
- 配套软件栈：CUDA / CANN / MUSA 版本与开放程度。
- 未声明芯片型号与代际时，禁止产出任何算力、显存、互联相关的比较结论。

## 上下文加载顺序（Context Budget）
1. 目标芯片规格表（含来源级别标注）。
2. 竞品对照芯片的同口径规格。
3. 下游约束：目标模型结构（稠密/MoE、专家数）、显存需求、互联需求。
4. 路标时间表（用于交付节奏判断）。
- 新闻报道与自媒体数据不直接进上下文，仅保留经核验的 A/B 级条目。

## 工具契约
- 参数比对输出必须为结构化表格，每行附来源与级别。
- 口径冲突必须并列（如 Rubin HBM4 总带宽 1,400 vs 1,580 TB/s），不得择一默认。
- "初步规格"（Preliminary information）必须保留该限定词直至规格转正。

## 任务执行流程（SOP）
- S1 需求解析：把选型需求分解为算力、显存、互联、格式、生态五维。
- S2 口径统一：确认对比双方使用同口径（密集 vs 稀疏、BF16 vs FP8）。
- S3 候选生成：产出候选芯片组合，附五维对照与缺口说明。
- S4 预算测算：显存承载（模型 + KV Cache + 激活）、互联带宽需求测算。
- S5 风险评估：代际交付风险、生态迁移成本、格式支持缺口。
- S6 证据打包：来源、级别、口径、日期齐备。
- S7 人工确认：采购类建议进入人工决策队列。

## 验证与证据要求
- 算力结论必须注明精度口径与密集/稀疏；显存结论必须注明容量与带宽两项。
- 带宽与算力不得跨口径直接比较（如 FP4 稀疏 vs BF16 密集）。
- 路标时间表注明"发布口径"或"预告口径"。
- 实测类结论仅可引用论文或基准实测（如 arXiv 2506.12708），发布会数字标注为发布口径。

## 失败与升级策略
- 关键参数仅获 C 级来源 → 输出 [待核实] 并暂停比较结论。
- 口径无法统一 → 输出并列对照，升级人工判断。
- 生态适配缺口无法量化 → 升级为 PoC 验证任务。

## 安全与合规红线
- 出口管制议题保持中性转述，不引用未经核实的条款编号。
- 不将单一厂商发布口径作为通用事实陈述。
- 引用第三方出货数据（如 IDC）须注明为转述并建议查原始报告。

## 禁止事项
- 禁止编造芯片型号、规格、路标日期。
- 禁止把初步规格写成正式规格、把发布口径写成实测。
- 禁止虚构标准编号（HBM/UCIe/UALink 等组件级标准除外，须写明标准属组件级）。
- 禁止残留 XX、___ 等非标准占位符。

## 输出格式
- 首行：可判定结论（通过 / 不通过 / 部分通过 + 阻塞项）。
- 五维对照表：算力 / 显存 / 互联 / 格式 / 生态，每维附来源级别。
- 口径声明：密集/稀疏、精度格式、实测/发布/初步规格。
- 待人工确认项：选型建议、采购节奏。
- 数值规范：参数带单位；范围用 ~ 连接；百分比数值与 % 之间不留空格。

## 评估与自检
- 每个参数是否都有来源与级别？
- 口径冲突是否并列而非择一？
- 初步规格是否保留限定词？
- 是否存在跨口径比较？
- 输出是否残留非标准占位符？

4.2. SKILL.md Specification

4.2.1. SKILL.md (AI Infra Group · AI Chip Selection Comparison and Baseline Verification)

---
name: ai-chip-selection-and-calibration
description: AI Infra 组芯片方向标准技能——芯片选型五维比对与参数口径核验。
  当需要进行 GPU/NPU 选型比对、核验芯片参数口径、测算显存与互联预算、
  评估数据格式适配时使用。触发词：芯片选型、HBM 带宽、NVLink/UB/UALink、
  FP8/MXFP4/HiF8、路标。
version: 1.0
created: 2026-09-12
---

# AI Infra 组 · AI 芯片选型比对与口径核验

> 本文为基于行业实践提炼的建议稿，非官方行业标准原文。
> 上位规范：01-AI-Infra组/AGENTS.md。

## 适用场景
- 训练/推理集群的加速器选型比对（含国产与海外路线）。
- 芯片参数口径核验（来源级别、密集/稀疏、初步规格标注）。
- 显存承载预算：模型权重 + KV Cache + 激活值是否超单卡/单机上限。
- 互联预算：目标并行策略（TP/EP）所需的 Scale-up 带宽是否满足。
- 数据格式适配：目标框架与模型是否支持 FP8/MXFP4/HiF8 等格式。

## 前置条件
- 已声明目标芯片型号与代际、配套软件栈版本。
- 已知目标模型结构（稠密/MoE、参数量、专家数）与上下文长度需求。
- 具备候选芯片的 A/B 级规格来源（官方产品页、发布会实录、论文实测）。

## 输入
| 输入项 | 说明 | 必需 |
|---|---|---|
| 目标模型需求 | 参数量、专家数、上下文长度、并行策略意向 | 是 |
| 候选芯片规格表 | 含来源与级别标注的规格清单 | 是 |
| 软件栈约束 | CUDA/CANN/MUSA 版本、框架支持矩阵 | 是 |
| 路标时间表 | 各候选代际的发布/上市时间与口径 | 否 |
| 预算与交付约束 | 采购预算、交付时间窗 | 条件必需 |

## 输出
| 输出项 | 说明 | 必需 |
|---|---|---|
| 可判定结论 | 通过 / 不通过 / 部分通过 + 阻塞项 | 是 |
| 五维对照表 | 算力/显存/互联/格式/生态，每维附来源与级别 | 是 |
| 显存预算表 | 权重 + KV Cache + 激活 vs 单卡/单机显存 | 是 |
| 互联预算表 | 并行策略带宽需求 vs 芯片互联能力 | 是 |
| 口径冲突清单 | 两口径并列 + [待核实] 标注 | 条件必需 |
| 待人工确认项 | 选型建议、采购节奏 | 是 |

## 执行步骤
1. 需求解析：把模型需求换算为算力、显存、互联、格式四类硬约束。
2. 口径统一：核对候选规格是否同口径（密集/稀疏、精度格式），不同口径分别列出。
3. 五维比对：生成结构化对照表，逐项标注来源级别（A/B/C）。
4. 显存预算：按目标模型与上下文长度测算权重、KV Cache、激活值占用。
5. 互联预算：按并行策略测算 TP/EP 所需带宽，对照芯片 Scale-up 能力。
6. 格式核验：确认目标框架对候选数据格式的支持矩阵。
7. 风险评估：代际交付风险、生态迁移成本、口径冲突汇总。
8. 交付：结论 + 对照表 + 冲突清单 + 待人工确认项。

## 质量标准（DoD）
- 每个参数有来源与级别；口径冲突并列；初步规格保留限定词。
- 显存与互联预算给出计算过程与假设。
- 无跨口径比较；无数值编造；无残留非标准占位符。
- 参照口径（不得直接套用）：昇腾 910C 封装 752 TFLOPS 密集 BF16、128 GB、
  每 die UB 392 GB/s（A级，arXiv 2506.12708 实测口径）；昇腾 950DT 144 GB /
  4 TB/s、互联 2 TB/s（A级，发布口径）；Rubin 288 GB HBM4 / 22 TB/s（A级，
  初步规格）。

## 常见失败与处理
| 失败模式 | 现象 | 处理 |
|---|---|---|
| 口径混比 | FP4 稀疏对比 BF16 密集 | 分列不同精度口径，禁止换算合并 |
| 初步规格固化 | 把 Preliminary information 写成正式规格 | 保留限定词，标注 [待核实] |
| 来源缺级 | 关键参数只有自媒体来源 | 标 C 级 [待核实]，暂停比较结论 |
| 显存漏项 | 预算只算权重漏掉 KV Cache | 强制三项分列（权重/KV/激活） |
| 路标当承诺 | 把预告日期写成确定交付 | 标注"发布口径/预告口径" |

## 示例
任务：为 MoE 模型（专家数 320、上下文 128K）在某国产超节点体系与某海外
机架级体系间做显存与互联适配初判。
1. 需求解析：320 专家 → EP 并行 → 高 Scale-up 带宽需求；128K 上下文 →
   KV Cache 显存需求显著。
2. 口径统一：候选 A（910C 级）用论文实测口径；候选 B（Rubin 级）用
   产品页初步规格口径，分别标注。
3. 五维比对：A 显存 128 GB / 封装、UB 互联、INT8 路线；B 显存 288 GB
   HBM4 / 22 TB/s、NVLink 6、NVFP4 路线；各标级别。
4. 显存与互联预算：给出权重/KV/激活三项测算与 EP 带宽测算。
5. 风险：A 依赖系统级组合弥补单卡差距（参照 CM384 案例）；B 为初步规格。
6. 交付：部分通过——两条路线均可行但假设不同，显存预算需按最终并行
   策略复核；冲突清单与待确认项齐备。

4.3. Landing Checklist

5. Summary

AI chips are the physical foundation of the L2 execution layer in the Harness six-layer model; the transmission to L1 (memory determines context carrying capacity) and to L5 (data formats determine the feasible region of the accuracy–performance tradeoff) are the most direct. Three conclusions:

1. Roadmaps are planning tools. Both the overseas (Rubin 2026 H2 → Rubin Ultra 2027 H2) and domestic (950PR/950DT → 960 → 970) roadmaps have entered a "one generation per year" cadence; cluster selection must treat delivery cadence as a first-class variable.
2. Baseline discipline is the foundation of credibility. This direction has the highest density of conflicting baselines (Rubin HBM4 total bandwidth 1400/1580 TB/s side by side, and the risk of mixing measured and published baselines); every number must state its source level and baseline nature.
3. "System compensates for single points" is the established strategy of the domestic route. The 910C measurement (arXiv 2506.12708) proves that single-chip parameters can be partly compensated through system interconnect and quantization strategies; domestic chips should be evaluated on the "chip + interconnect + framework" system baseline to avoid distortion from single-point comparison.

Information Gap Statement

The following entries have not been confirmed by Level A/B sources and are marked [To be verified] in the body text:

1. No IEEE/ISO/JEDEC dedicated standard for the AI chip runtime side was found in this direction; HBM, UCIe, UALink etc. are component-level/interconnect standards and must be honestly described as such when writing; standard numbers must not be invented.
2. Rubin NVL72 HBM4 total bandwidth conflicts between 1,400 TB/s and 1,580 TB/s (both from NVIDIA pages), shown side by side, both marked [To be verified].
3. No public benchmarks of Rubin versus Blackwell (MLPerf or third-party measurements) were found as of 2026-09-12.
4. All Ascend 950/960/970 figures are published baselines, with no independently measured MFU/ETTR-type metrics.
5. IDC shipment data (4 million units total; 812,000 Ascend) are relayed through media; consulting the original IDC report is recommended; the other-domestic-vendors share is a derived figure.
6. Xinlian Technology's UALink IP (112G in production, 224G taped out) and the Biren ODCC interoperability test are from industry-analysis articles, Level C; each citation needs its source re-verified.
7. NVIDIA Groq 3 LPX's "35× per-watt inference improvement" is a vendor-claimed baseline.
8. No public AGENTS.md/SKILL.md standard exemplar for this direction was found; this article is a draft proposal.

6. References

1. Leading a new paradigm for AI infrastructure with pioneering supernode interconnect technology (Xu Zhijun HC2025 keynote, incl. Ascend roadmap) — Huawei, 2025-09-18. https://www.huawei.com/cn/news/2025/9/hc-xu-keynote-speech
2. Serving Large Language Models on Huawei CloudMatrix384 — Huawei/SiliconFlow, arXiv 2506.12708, 2025-06. https://arxiv.org/pdf/2506.12708
3. NVIDIA Vera Rubin NVL72 product page (preliminary specifications) — NVIDIA, 2026-03. https://www.nvidia.com/en-us/data-center/vera-rubin-nvl72/
4. NVIDIA Vera Rubin Opens Agentic AI Frontier (GTC 2026 press release) — NVIDIA, 2026-03. https://investor.nvidia.com/news/press-release-details/2026/NVIDIA-Vera-Rubin-Opens-Agentic-AI-Frontier/
5. NVIDIA Vera Rubin POD: Seven Chips, Five Rack-Scale Systems — NVIDIA Developer Blog, 2026-03. https://developer.nvidia.com/blog/nvidia-vera-rubin-pod-seven-chips-five-rack-scale-systems-one-ai-supercomputer/
6. UALink 1.0/2.0 specification releases (2025-04 / 2026-04, multi-source cross-check) — UALink Consortium. https://ualinkconsortium.org/
7. Research on key supernode technologies and industry development trends — Chinese Society of Thermal Physics (repost), 2025–2026. https://www.zgcsswdx.cn/info/24724.html
8. Multiple AI Scale-Up Options Emerge (NVLink Fusion/ESUN/UALink boundary analysis) — SemiEngineering. https://semiengineering.com/multiple-ai-scale-up-options-emerge/
9. 2025 China AI accelerator card shipments (citing IDC) — Sina Finance. https://finance.sina.com.cn/jjxw/2026-09-02/doc-iniqmmyw1388522.shtml
10. AI Infra (design side, cross-referencing chip specs and domestic landscape) — 02-行业赋能/04-硬件研发组/05-ai-infra.md, 2026-09-12.