Test

1. Introduction

1.1. Background

Chip testing bridges design and mass production, serving as the final gate for quality and cost. Its core economic pressure can be captured by a set of figures: yield loss plus test cost together can account for 20%~30% of total production cost (McKinsey, cited via the Netguru case study, level B-, marketing content, figures should be stated cautiously).

The test phase has long faced three tensions:

1. Coverage vs. time cost. The more test vectors, the more thorough the defect coverage, but the higher the test time cost. At the complexity of billions of transistors at advanced nodes, traditional static test methods and rule-based yield management systems are no longer sufficient to meet high-volume quality, throughput, and cost targets.
2. Data volume vs. analytical capability. The manufacturing side generates a huge amount of data that is not systematically analyzed, and data sources are not connected across tool groups.
3. Compression vs. diagnosis. Compressing the test set can save money, but it may lose the ability to localize failures — and "diagnosis preservation" happens to be one of the least studied directions in academia.

1.2. Definition and Scope

The test direction covers the entire process from design-for-testability to volume test and failure analysis; in the AI Harness context it specifically refers to what is participated in or led by agents:

Boundary with the verification direction: verification targets design correctness and is a pre-silicon activity; testing targets manufacturing defects and is a post-silicon activity. The two converge at the fault-simulation stage — Siemens Questa One's fault simulation supports both functional-safety fault simulation and DFT fault simulation; IEEE 1838's 3D DFT architecture in turn relies on IEEE 1687 IJTAG and the IEEE 1500 wrapper.

1.3. Positioning in the AI Harness System

图 1-1｜芯片测试方向在 AI Harness 体系中的定位：L1–L6 层栈

数据来源：基于本文分析绘制的示意图。

Core judgment: the bottleneck of the test direction lies in the L6 governance and safety layer. Yield data and test programs are among the manufacturing enterprise's most valuable assets and are forbidden from leaving the factory network boundary; the automotive scenario also carries the mandatory ISO 26262-11:2018 compliance constraint. This means the Harness for the test direction must first solve "where the data is computed" and only then "whether the algorithm is good".

A key structural advantage: test is one of the earliest to mature for AI/ML application in the hardware domain. The reason is that the manufacturing side gives AI fast and accurate feedback — every wafer produced is a labeled sample, and metrology equipment reports line width and defect location on the spot; whereas on the design side, the correctness of a tape-out is only known months later when the chip comes back (this comparison comes from a Chinese technical analysis, level C, but it has reference value as a core argument explaining "why AI lands faster in test and manufacturing").

1.4. Current State of Development

1.4.1. Current State of Technical Standards

1.4.2. Key Quantitative Parameters

1.4.3. Additional Requirements for Automotive Functional Safety on Testing

"Road vehicles — Functional safety — Part 11: Guideline on the application of ISO 26262 to semiconductors" (ISO 26262-11:2018) is the application guideline in the ISO 26262 family specifically addressing semiconductors. It was published in 2018-12, comprises 179 pages in total, and is informative, not normative in nature.

Its content structure is: failure-rate estimation (15 pages), DFA dependent-failure analysis (16 pages), digital components and memory (19 pages), analog and mixed signal (17 pages), FPGA (16 pages), multi-core (5 pages), sensors and converters (14 pages), plus examples such as DMA-mode safety-mechanism analysis, MCU dependent-failure analysis, analog-regulator dependent-failure analysis, FME(D)A of CPU+RAM, FME(D)A of LDO, and PLD failure-rate allocation.

Points directly relevant to testing:

• Safety-mechanism classification and evaluation guidance: dual-core lockstep, ECC, BIST, clock/voltage/temperature monitoring, watchdog timers, and so on; it requires not only sufficient diagnostic coverage but also consideration of the failure possibility of the safety mechanisms themselves.
• Fault models: permanent faults of digital circuits such as stuck-at, open circuit, and bridging; transient faults such as SET, SEU, and MBU; memory fault models; soft errors (single-event upsets).
• Three hardware-architecture metrics: SPFM, LFM, PMHF (ASIL D corresponds to 10 FIT).
• SEooC (Safety Element out of Context) and the AoU (Assumptions of Use) assumptions-list mechanism: the chip supplier develops against assumptions, and the integrator must verify each assumption holds.
• IP-core qualification and integration: clarifies the boundary of responsibility between the IP provider and the system integrator.

2. Glossary

3. Case Studies

3.1. Advantest ACS RTDI and NVIDIA AI

Evidence level: A (official Advantest news / HPCwire / Quantum Zeitgeist)

3.1.1. Background

For decades, chip makers had to spend weeks collecting test data, analyzing failures, and iterating on test scripts before they could decide whether a wafer could ship. This is the cornerstone of quality assurance, and a major bottleneck in an era where every microsecond counts.

3.1.2. Solution

Announced in San Jose on 2025-10-06. Advantest Cloud Solutions Real-Time Data Infrastructure (ACS RTDI) integrates NVIDIA machine learning, and its Harness architectural characteristics are highly instructive:

• Data flow: factory sensors send raw data streams directly to the NVIDIA AI inference engine (Blackwell GPU) for signal-by-signal real-time analysis.
• Closed-loop mechanism: through a Data-Feed-Forward cross-insertion mechanism, the GPU continuously refines the test set for each chip, adapting to specific manufacturing conditions and material variation.
• Three-layer decoupling (a textbook design for L3 orchestration): the architecture deliberately separates the data-preparation, algorithm-modeling, and decision layers, letting the production operator replace or upgrade any single component without overhauling the whole system — when changing process nodes, chip architectures, or quality targets, it can be reconfigured in minutes rather than months.
• Deployment fact: NVIDIA has selected ACS RTDI for high-volume production of its Blackwell and next-generation devices.

Subsequent plans: bring NVIDIA NeMo and NIM microservices into the ACS semiconductor test-analysis offering to govern heterogeneous production data (lithography images, electrical measurements, environmental logs), evaluate models, and deploy generative-AI agents within the test environment — these agents can propose new test patterns, simulate defect scenarios, and even generate firmware patches to mitigate identified issues, all without human intervention.

3.1.3. Results

• The scalable GPU architecture supports concurrent training of multiple ML models for uninterrupted operation.
• Early pilots reportedly report latency reductions of up to 30% and test-budget cost savings of over 15% (as reported by Advantest).
• Reduced test coverage also brings lower power consumption, shorter test time, and a smaller carbon footprint.

Implications for Harness in this direction: three-layer decoupling (data preparation / algorithm modeling / decision) is an architectural principle that can be borrowed directly. It lets models be upgraded independently without rebuilding the entire production data pipeline — precisely the core value of Harness in long-lifecycle industrial systems.

3.2. DFT Engineering Practice for 3D IC and Chiplet

Evidence level: B+ (3D InCites) / B (EE World Online citing Keysight)

3.2.1. Background

3D stacking brings four challenges not encountered in traditional 2D testing:

1. Some die pins cannot be accessed by ATE probes, so individual die must be thoroughly tested at the wafer level.
2. How to access any die within the package.
3. Usually only the bottom die has boundary scan.
4. Intra-die and inter-die failure diagnosis needs to be automated.

3.2.2. Solution

Siemens EDA's approach is built on hierarchical DFT + an IEEE 1687-compliant IJTAG network + Streaming Scan Network (SSN, bus-based packetized testing):

• Die level: die wrap cell analysis and insertion let IOs not directly probed by ATE be controlled and observed instead via the DWR (die wrapper register).
• Probe accessibility: sacrificial PADs are designed for the TAP, FPP, clock, and power pins for use by wafer probes, and are discarded during stacking.
• Die-to-die communication: the IEEE 1838 master/slave TAPs handle die-to-die communication.
• Bus compatibility: SSN's flexible bus width natively supports the most novel FPP part of IEEE 1838.
• Automation: the IJTAG network and languages (ICL + PDL) are used to operate and automate the entire DFT setup; die-to-die ATPG treats each die as a gray box wrapped by the DWR.

In terms of the test flow, a chiplet must go through the full stages: design-time simulation → KGD test before stacking → intermediate bonding test → post-bond test after stacking → final test of the packaged product → system-level test.

UCIe PHY-layer simulation verification points (as reported by Keysight): ① supports the UCIe PHY standard, including automatic signal parsing and automatic multi-die connection; ② precisely computes and verifies that the voltage transfer function (VTF) conforms to the UCIe specification, including system bit-error-rate (BER) analysis and quantification of eye-diagram parameters (height, width, skew, mask margin); ③ precisely analyzes the forward clock to capture asynchronous behavior.

3.2.3. Results

• The hierarchical DFT approach can retarget test patterns created at the sub-die / die level (BIST or scan patterns) to package-level testing.
• Diagnostics based on hierarchical DFT natively support identifying inter-die and intra-die failures.

Heterogeneous challenges: chiplets mix multiple process nodes and materials; each die has different thermal characteristics, responds differently to EMI, and faces performance challenges such as electromigration.

3.3. Survey of Machine-Learning Adaptive Testing and Yield Optimization

Evidence level: B (Research Square preprint, not peer-reviewed by a journal)

3.3.1. Background

At the complexity of billions of transistors at advanced nodes, traditional static test methods and rule-based yield management systems are no longer sufficient to meet high-volume quality, throughput, and cost targets.

3.3.2. Solution

A systematic review of 21 primary sources from 2019~2025 (IEEE conference papers, journal articles, and industry technical publications) covering three major themes: adaptive test optimization, machine-learning-enhanced outlier detection and limit setting, and diagnosis preservation during test-time reduction.

3.3.3. Results

Quantitative conclusions:

• GPR (Gaussian Process Regression) outperforms the classic algorithm DPAT (Dynamic Part Average Testing) for spatial outlier detection on real production wafer data.
• The conformal prediction framework provides calibrated Vmin intervals with about 90% theoretical coverage guarantee on industrial 5nm automotive chips.
• Machine-learning adaptive testing: test-time reduction of about 25% while preserving defect coverage.
• Unsupervised learning: reduced customer-escape DPPM relative to DPAT/NNR baselines on 6 automotive MCU datasets.
• SHAP interpretability: delivered a 21.7% yield-loss reduction in a controlled field experiment.

Open gaps explicitly listed by the authors (highly valuable and directly writable into an upgrade strategy):

1. Lack of standardized data-sharing protocols.
2. Limited peer-reviewed research on "diagnosis preservation during test reduction".
3. Insufficient research on model generalization across process nodes.

Citation note: the source for this case is a preprint that has not undergone journal peer review; please note this when citing.

4. Practice Standards

Nature statement: the AGENTS.md and SKILL.md below are draft proposals distilled from public industry practice and are not the text of official industry standards. As of the writing of this document, no publicly available AGENTS.md or SKILL.md standard template aimed at the chip-testing direction was found.

4.1. AGENTS.md Specification

4.1.1. AGENTS.md (Test Direction)

# AGENTS.md —— 测试

> 本文为基于行业实践提炼的建议稿，非官方行业标准原文。

## 角色与边界
- 角色：芯片测试智能体，负责 DFT 架构辅助、测试程序优化、自适应测试策略、
  良率根因分析与失效定位辅助。
- 判定器为 ATE 与量测设备：所有 DPPM、良率、故障覆盖率结论必须由真实机台或
  量测数据给出，模型不得推断。
- 不负责：量产放行签字、测试限值（test limit）的最终放宽决定、ASIL 等级判定。
- 测试限值的任何放宽必须走人工审批，智能体只能提出建议。

## 环境假设
执行前必须显式声明：
- ATE 机台型号与软件版本；探针台配置；多站点能力。
- DFT 架构：扫描链结构、压缩配置、BIST、IEEE 1687 合规 IJTAG 网络、SSN 总线宽度。
- 测试访问标准族：IEEE 1149.1（1990 年首发）/ 1149.6 / 1500 / 1687（2014 年发布）/
  IEEE Std 1838-2019。
- 3D 堆叠场景须声明：主/从 TAP 配置、DWR 结构、FPP 宽度、sacrificial PAD 方案。
- 产品类型与工艺节点；车规场景须声明目标 ASIL 等级与 ISO 26262-11:2018 适用条款。
- 数据驻留位置：良率数据与测试程序是否允许离开工厂网络；允许的计算环境边界。
- 未声明机台与 DFT 架构时，禁止产出与测试时间、覆盖率、DPPM 相关的任何结论。

## 上下文加载顺序（Context Budget）
1. 测试规范与测试计划、当前测试程序与限值表。
2. DFT 结构描述（扫描链、IJTAG 网络、BIST 配置）。
3. 近期良率摘要、晶圆图索引、失效样本库条目。
4. 历史根因分析与已关闭缺陷记录。
5. 产品与工艺变更记录（换节点、换材料、换设备均须纳入）。
- 完整晶圆图、全量 ATE 日志不进上下文，以路径引用 + 工具查询代替。

## 工具契约
- 优先为 ATE 控制接口、诊断工具、良率分析系统封装 MCP 服务器。
- 工具返回值必须包含：退出码、日志路径、关键指标数值、机台编号、软件版本。
- 测试程序变更必须可回滚，且保留上一版本与差异说明。
- 模型推理必须在允许的计算环境内执行，不得把良率数据传输至未授权位置。
- 不可逆工具（量产程序下发、限值全局生效）默认不授予直接调用权限。

## 任务执行流程（SOP）
- S1 需求解析：把测试目标分解为可判定子目标（测试时间、故障覆盖率、DPPM）。
- S2 基线建立：记录基线测试时间、良率、DPPM、故障覆盖率。
- S3 候选生成：产出候选测试项裁剪、限值调整、采样策略，每个附理由与预期影响。
- S4 机台判定：在受控批次上执行，得到客观数值。
- S5 差异分析：与基线对比，**必须同时评估诊断能力是否保留**。
- S6 合规校验：车规场景校验安全机制诊断覆盖率与故障注入结果。
- S7 证据打包：命令、脚本、日志路径、机台编号、数值、版本齐备。
- S8 人工确认：测试限值与量产放行进入人工审批队列。

## 验证与证据要求
- 测试压缩必须同时报告：压缩倍数、故障覆盖率变化、DPPM 与客户逃逸率是否恶化、
  诊断能力是否保留。四者缺一不可。
- 模型输出须附不确定性说明：涉及限值的预测须给出区间估计，不得只给点估计。
- 跨工艺节点复用模型时，必须重新验证泛化性并报告漂移情况。
- 良率根因结论须给出可解释性分析（如特征贡献度），不得只给黑箱结论。
- 车规场景须校验三项硬件架构度量：SPFM、LFM、PMHF。
- 每条结论须附：工具名 + 版本 + 命令或脚本 + 日志路径 + 关键数值 + 机台编号。

## 失败与升级策略
- DPPM 或客户逃逸率出现恶化趋势 → 立即停止测试压缩类动作，回滚至上一基线。
- 模型在新工艺节点上表现显著偏离 → 停止自动决策，升级人工并重训或重标定。
- 诊断能力下降（无法定位到已知失效样本）→ 停止压缩，恢复诊断相关测试项。
- 数据来源存疑或样本量不足 → 升级人工，不得用小样本支撑全局结论。
- 升级时须交付：已完成证据包 + 失败点定位 + 下一步可执行的具体命令。

## 安全与合规红线
- 良率数据、测试程序、晶圆图属制造核心资产，**不得离开工厂网络边界**，
  不得作为外部模型的训练输入。
- 自主智能体必须在隔离运行时内执行。
- 测试限值的任何放宽必须有书面理由与批准记录；禁止为提升良率数字而放宽限值。
- 车规场景须符合 ISO 26262-11:2018：安全机制诊断覆盖率、故障注入、FMEDA、
  SPFM / LFM / PMHF、软错误（SEU / SET / MBU）分析；
  SEooC 的 AoU 假设清单须逐条验证。
- 所有工具调用、限值变更、人工确认写入不可篡改审计日志。
- 数据准备、算法建模、决策三层应解耦，便于单独替换或升级任一组件
  （参考 Advantest ACS RTDI 架构原则）。

## 禁止事项
- 禁止编造或臆测良率、DPPM、故障覆盖率、测试时间数值。
- 禁止输出"应该没问题""大概率覆盖"等不可判定表述。
- 禁止为提升良率数字而放宽测试限值。
- 禁止在诊断能力未验证的情况下全面推行测试压缩。
- 禁止把良率数据与测试程序传输至未授权位置。
- 禁止用小样本结论支撑全局决策。
- 禁止虚构标准编号；未确认标准一律标注 [待核实]。
- 禁止在无人确认下触发量产程序下发与限值全局生效。

## 输出格式
- 首行给出可判定结论（通过 / 不通过 / 部分通过 + 阻塞项）。
- 证据表：工具、版本、命令或脚本、日志路径、机台编号、关键数值、与基线差值。
- 四象限报告：测试时间、故障覆盖率、DPPM、诊断能力同时列出。
- 不确定性说明：模型给出的限值或预测须附区间估计与样本量。
- 风险与假设：列出结论依赖的工艺节点、批次范围、样本量。
- 待人工确认项：限值放宽、量产放行、跨域权衡。
- 数值规范：参数带单位；范围用 ~ 连接；百分比数值与 % 之间不留空格。

## 评估与自检
- 本轮所有数值是否来自真实机台或量测输出？
- 测试压缩是否同时评估了诊断能力保留？
- DPPM 与客户逃逸率是否恶化？
- 是否给出不确定性区间而非仅点估计？
- 跨节点复用时是否重新验证了泛化性？
- 是否存在未经批准的限值放宽？
- 良率数据是否发生过越界传输？
- 输出中是否残留 XX、___ 等非标准占位符？
- Harness 或提示词变更后，是否在固定黄金样本集上回归并报告与上一版本的差值？

4.2. SKILL.md Specification

4.2.1. SKILL.md (Test · Adaptive Test Optimization and Yield Root Cause Analysis)

---
name: test-adaptive-and-yield-rca
description: 测试方向的自适应测试优化与良率根因分析技能。当需要在保持缺陷覆盖的前提下
  压缩测试时间、做空间离群点检测与限值标定、定位良率损失根因，并要求 DPPM 与客户逃逸率
  不恶化、诊断能力保留时使用。
version: 1.0
created: 2026-09-12
---

# 测试 · 自适应测试优化与良率根因分析

> 本文为基于行业实践提炼的建议稿，非官方行业标准原文。

## 适用场景
- 测试时间过长导致成本压力，需要在保持缺陷覆盖前提下压缩。
- 静态限值导致过杀（overkill）或逃逸（escape），需要动态限值标定。
- 晶圆图上出现空间相关性缺陷模式，需要离群点检测。
- 良率突降或缓慢退化，需要根因定位与可解释性分析。
- 3D IC 与 Chiplet 场景的 DFT 架构验证与测试 pattern 重定向。
- 车规场景的安全机制诊断覆盖率评估与故障注入验证。

## 前置条件
- 已声明 ATE 机台与软件版本、DFT 架构、测试访问标准族。
- 存在基线数据：测试时间、良率、DPPM、故障覆盖率、逃逸率。
- 数据驻留位置与计算环境边界已明确，不得越界。
- 样本量足以支撑统计结论；小样本须显式标注。
- 智能体运行于隔离运行时。
- 具备判定器：ATE pass/fail、故障覆盖率、量测结果。

## 输入
| 输入项 | 说明 | 必需 |
|---|---|---|
| 测试规范与程序 | 当前测试项、限值表、执行顺序 | 是 |
| DFT 结构描述 | 扫描链、IJTAG 网络、BIST、SSN 配置 | 是 |
| 基线数据 | 测试时间、良率、DPPM、故障覆盖率 | 是 |
| 历史数据 | 晶圆图、ATE 日志、失效样本库 | 是 |
| 环境与工艺记录 | 工艺节点、材料变更、设备变更 | 是 |
| 样本量说明 | 统计结论所基于的样本规模 | 是 |
| 车规要求 | 目标 ASIL 等级与安全机制清单 | 条件必需 |

## 输出
| 输出项 | 说明 | 必需 |
|---|---|---|
| 可判定结论 | 通过 / 不通过 / 部分通过 + 阻塞项 | 是 |
| 四象限报告 | 测试时间、故障覆盖率、DPPM、诊断能力 | 是 |
| 不确定性说明 | 区间估计、样本量、置信水平 | 是 |
| 根因分析 | 良率损失根因与可解释性分析 | 条件必需 |
| 变更清单 | 测试项增删与限值调整，附理由 | 是 |
| 证据表 | 工具、版本、命令或脚本、日志路径、机台编号、数值 | 是 |
| 待人工确认项 | 限值放宽、量产放行 | 是 |

## 执行步骤
1. 环境校验：核对机台、DFT 架构、标准族版本、数据驻留边界；缺失即停止。
2. 基线确认：确认基线测试时间、良率、DPPM、故障覆盖率与样本量。
3. 数据分析：做空间离群点检测、分布分析与相关性分析。
4. 候选生成：产出候选测试项裁剪、限值调整、采样策略，每个附理由与预期影响。
5. 受控验证：在受控批次上执行，记录命令、退出码、日志路径、机台编号。
6. 四象限评估：同时评估测试时间、故障覆盖率、DPPM、诊断能力。
7. 可解释性分析：给出特征贡献度，形成根因结论。
8. 合规校验：车规场景校验 SPFM、LFM、PMHF 与故障注入结果。
9. 证据打包与交付：列出待人工确认项，写入审计日志。

## 质量标准（DoD）
- 测试时间、故障覆盖率、DPPM、诊断能力四项同时报告，不得只报有利项。
- 缺陷覆盖未下降，DPPM 与客户逃逸率未恶化。
- 诊断能力经已知失效样本验证保留。
- 限值或预测给出区间估计与样本量，非仅点估计。
- 跨工艺节点复用前已重新验证泛化性并报告漂移。
- 良率根因结论附可解释性分析。
- 每条结论附工具名 + 版本 + 命令或脚本 + 日志路径 + 关键数值 + 机台编号。
- 无未经批准的限值放宽。
- 输出中无 XX、___ 等非标准占位符；未确定项统一标注 [待填写] 或 [待核实]。
- 参考阈值：机器学习自适应测试在保持缺陷覆盖前提下测试时间减少约 25%、
  SHAP 可解释性带来 21.7% 良率损失下降、conformal prediction 在工业 5nm 车规芯片上
  给出约 90% 理论覆盖保证的校准 Vmin 区间（级别 B，预印本）；
  Advantest ACS RTDI 早期试点延迟降低最高 30%、测试预算成本节省超 15%（级别 A）。

## 常见失败与处理
| 失败模式 | 现象 | 处理 |
|---|---|---|
| 过杀 | 合格品被判为不合格，良率虚低 | 复核限值标定，加入空间相关性建模 |
| 逃逸 | 缺陷品流出，DPPM 上升 | 立即回滚，恢复被裁剪的测试项 |
| 诊断能力丢失 | 压缩后无法定位已知失效 | 恢复诊断相关测试项，重新验证 |
| 跨节点失效 | 模型换工艺节点后表现骤降 | 停止自动决策，升级人工并重训或重标定 |
| 小样本过拟合 | 结论在扩容后不成立 | 标注样本量，扩充后重新验证 |
| 黑箱结论 | 根因无法解释，工程上不可执行 | 补充可解释性分析后再交付 |
| 数据越界 | 良率数据被传至未授权位置 | 立即中断并上报 |
| 限值漂移 | 长期运行后限值缓慢放宽 | 建立限值变更审批与定期复核机制 |

## 示例
任务：某车规 MCU 测试时间过长，需在保持缺陷覆盖前提下压缩 20%，且 DPPM 不恶化。
1. 环境校验：确认 ATE 机台与软件版本、扫描链与 IJTAG 配置、车规 ASIL 等级、数据驻留边界。
2. 基线确认：记录基线测试时间、良率、DPPM、故障覆盖率与样本量（不少于 10 个批次）。
3. 数据分析：做空间离群点检测（GPR 对比 DPAT 基线）与测试项贡献度分析。
4. 候选生成：产出测试项裁剪方案 A（裁剪低贡献项）与方案 B（动态限值 + 采样）。
5. 受控验证：在 3 个受控批次上执行，记录机台编号、日志路径、数值。
6. 四象限评估：方案 A 测试时间 -22%、故障覆盖率持平、DPPM 未恶化、
   但 1 类已知失效样本无法定位；方案 B 测试时间 -18%、四项均达标。
7. 可解释性分析：给出对良率损失贡献最大的三个测试项与两个工艺参数。
8. 合规校验：校验 SPFM、LFM、PMHF 仍满足目标 ASIL 等级要求。
9. 交付：结论"部分通过，推荐方案 B；方案 A 因诊断能力丢失不予采纳"；
   证据表含机台编号、命令、日志路径、数值、样本量、与基线差值。

## 关联
- 与验证方向的边界：验证面向设计正确性（pre-silicon），测试面向制造缺陷（post-silicon）；
  两者在故障仿真环节合流。
- 与封装方向的耦合：Chiplet 必须先 KGD 才能堆叠；UCIe 2.0 的 UDA 把测试、遥测、
  调试内置进 chiplet，覆盖从 sort 到现场的全生命周期。
- 与 AI Infra 的耦合：Advantest ACS RTDI 把 NVIDIA AI 推理引擎引入产线，
  是 AI Infra 技术反哺半导体测试的实例。

4.3. Implementation Checklist

5. Summary

The test direction is one of the earliest maturing application areas for AI/ML in the hardware domain. The root reason is that the manufacturing-side feedback loop is fast and accurate: every wafer produced is a labeled sample, and metrology equipment reports line width and defect location on the spot; on the design side, in contrast, the correctness of a tape-out is only known months later when the chip comes back (this comparison comes from a Chinese technical analysis, level C).

Three engineering principles for this direction:

1. Compression must not sacrifice diagnostic capability. Test time, fault coverage, DPPM, and diagnostic capability must form a joint four-quadrant evaluation; any degradation triggers a rollback. Academia has explicitly noted that "diagnosis preservation during test reduction" is a direction with insufficient peer-reviewed research, so engineering practice should verify it explicitly.
2. Models must provide uncertainty. Predictions involving limits must give interval estimates rather than point estimates. Conformal prediction provides calibrated Vmin intervals with about 90% theoretical coverage guarantee on industrial 5nm automotive chips — a method path worth borrowing.
3. Architecture must be three-layer decoupled. Advantest ACS RTDI deliberately separates the data-preparation, algorithm-modeling, and decision layers, allowing reconfiguration in minutes rather than months when changing process nodes or chip architectures — this is the core value of Harness in long-lifecycle industrial systems.

At the governance level, the bottom line of the test direction is: yield data and test programs must not leave the factory network boundary, and any relaxation of test limits must have written justification and an approval record. The automotive scenario must also satisfy ISO 26262-11:2018's requirements on diagnostic coverage, fault injection, and the three hardware-architecture metrics.

Three research gaps that must be honestly noted: the lack of standardized data-sharing protocols; insufficient research on diagnosis preservation during test reduction; and insufficient research on model generalization across process nodes. These three are both academic gaps and real constraints on Harness deployment in this direction.

Information Gap Statement

The following items have not been confirmed by A-level or B-level sources and are marked [To be verified] in the body text:

1. Teradyne multi-site probe station: parallel test of 96 chiplets, approx. USD 12 million per unit (level C).
2. Netguru's citation of McKinsey's "yield-loss reduction of up to 30%" is marketing content; the figures should be stated cautiously (level B-).
3. The 98.2% accuracy of wafer-map defect classification and the 1.67 s per-wafer processing time are suspected to originate from AI-generated content; this document does not cite them (level C, source is a dev.to research summary).
4. The specific current revisions of IEEE 1149.1, IEEE 1149.6, IEEE 1500, and IEEE 1687 have not been confirmed on the IEEE website; this document only states the confirmed initial-release or publication years.
5. IEEE 1450.6.1 (OCI) has a status of Inactive - Approved; this must be noted when citing.
6. The specific revision of IEC 61508 has not been confirmed on the official page and is marked [To be verified].
7. ISO/SAE 21434 has not been confirmed on the official page and is marked [To be verified].
8. China's "training-cluster comprehensive performance evaluation standard" draft for comment (end of 2025) has low relevance to this direction, and is level C.
9. The comparison of "fast manufacturing-side feedback, slow design-side feedback" comes from a Chinese technical analysis, level C, cited as an opinion rather than factual data.
10. No publicly available AGENTS.md or SKILL.md standard template aimed at the chip-testing direction was found; this document is a draft proposal.

6. References

1. Advantest Pioneers a New Era of AI (ACS RTDI, 2025-10-06) — Advantest. https://www.advantest.com/en/news/2025/2025100602.html
2. Advantest ACS RTDI × NVIDIA report — HPCwire. https://hpcwire1stg.wpenginepowered.com?p=184054/
3. Advantest Pioneers a New Era of AI — Quantum Zeitgeist. https://quantumzeitgeist.com/advantest-pioneers-a-new-era-of-ai/
4. Machine Learning for Adaptive Test and Yield Learning (preprint) — Research Square. https://www.researchsquare.com/article/rs-9464431/v1
5. How AI Leads to a Reduction in Yield Detraction by up to 30% (citing McKinsey) — Netguru. https://www.netguru.co/blog/how-ai-leads-to-a-reduction-in-yield-detraction-by-up-to-30percent
6. IEEE 1838 Explained: How DFT Evolves for 2.5D, 3D and 3.5D ICs — LoveChip. https://www.lovechip.com/blog/ieee-1838-explained-how-dft-evolves-for-2-5d-3d-and-3-5d-ics
7. 3D IC / Chiplet DFT engineering practice — 3D InCites. https://www.3dincites.com/?p=76406
8. UCIe PHY simulation verification points (citing Keysight) — EE World Online. https://www.eeworldonline.com/?p=511270
9. Chinese Journal of Electronics English edition · 3D-stacked testing survey (CJE 2025). https://cje.ejournal.org.cn/article/doi/10.23919/cje.2025.00.160
10. ISO 26262-11:2018 Road vehicles — Functional safety — Part 11 — ISO. https://www.iso.org/fr/contents/data/standard/06/96/69604.html
11. Design And Reuse / IEEE joint page (status of standards such as IEEE 1450.6.1). https://us.design-reuse.com/exit/?urlid=9987
12. NVIDIA GB200 NVL72 — NVIDIA official site (background on Blackwell devices). https://www.nvidia.com/en-us/data-center/gb200-nvl72/
13. Accellera official site (standard and status lookup). https://accellera.org/
14. Siemens EDA Tessent official product page. https://eda.sw.siemens.com/en-US/ic/tessent/