Chip Verification

1. Introduction

1.1. Background

Chip verification is the most resource-intensive stage in digital chip development. RTL verification of complex SoCs accounts for 60%~70% of the project cycle; the verification team is typically 2~5 times the size of the RTL design team (this figure comes from secondhand reproduction). The industry calls this pressure the Verification Productivity Gap — design complexity grows exponentially, while the growth of verification manpower is linear.

In the era of 3D-IC, Chiplet architectures, and software-defined systems, this gap is further amplified (Siemens calls it Verification Productivity Gap 2.0): the complexity explosion is compounded by a shortage of senior engineers, while requirements for safety, power, reliability, and sustainability all rise across the board.

Verification has a key property that sets it apart from other hardware stages: its feedback loop is both cheap and decidable. The simulator gives a deterministic pass or fail signal, the coverage database can be read directly, and the regression suite produces thousands of runs every night. This is precisely the closed-loop structure a reinforcement-learning-style agent needs — and it is the fundamental reason why the first wave of Agentic AI in EDA is concentrated in verification, debugging, and coverage closure, rather than synthesis or place and route.

1.2. Definition and Scope

The chip verification direction covers all activities that confirm design correctness before tape-out; in the AI Harness context it specifically refers to those carried out with or led by agents:

Boundary with adjacent directions: verification targets design correctness, while test targets manufacturing defects. But the two converge in fault simulation — Siemens Questa One's fault simulation supports both functional-safety fault simulation and DFT fault simulation; and IEEE 1838's 3D DFT architecture in turn relies on IEEE 1687 IJTAG and the IEEE 1500 wrapper.

1.3. Position within the AI Harness Architecture

图 1-1｜芯片验证在 AI Harness 六层模型中的定位

数据来源：基于本文分析绘制的示意图。

Core judgment: chip verification is the direction in which the six-layer model's L5 evaluation and observation layer manifests most purely, for three reasons:

1. Coverage is a natural reward function. No need to design rewards manually; the coverage figure itself is the optimization target.
2. The simulator gives fast binary judgments. Pass or fail is clear, with no gray zone.
3. The regression suite provides a high-frequency closed loop. Thousands of runs each night, plenty of samples.

At the L2 layer, the verification direction has an important engineering advantage: there is no need to replace the existing infrastructure. Chip teams already have nightly-regression CPU farms, coverage databases, and Synopsys / Cadence / Siemens simulation and formal flows, on which the agent layer can be directly layered. Siemens' official 2026 position explicitly emphasizes "keeping the existing simulation engines hooked in rather than replacing them".

1.4. Current Status

Key insight: the Level-A (official first-hand) figures in the table above are concentrated in Siemens' and Cadence's official releases; the rest are customer-measured figures, mostly compiled from Chinese technical communities' summaries of SNUG / DVCon shares and require verification. When writing and citing, these must be strictly distinguished — Level-C figures must not be treated as official statements.

Related technical standards:

2. Glossary

3. Case Studies

3.1. Siemens Questa One and Agentic Toolkit

Evidence level: A (Siemens official release and official interview)

3.1.1. Background

Siemens defines the current challenge as Verification Productivity Gap 2.0: the complexity explosion brought by 3D-IC, Chiplet architectures, and software-defined systems, compounded by a shortage of senior engineers and rising requirements for safety, power, reliability, and sustainability. In the traditional verification flow, most of a verification engineer's time is spent on "isolated tool interactions" — manually invoking lint, manually writing constraints, manually analyzing coverage, manually debugging — and the context between each step has to be carried around manually.

3.1.2. Solution

Siemens released the Questa One intelligent verification product portfolio on 2025-05-15 (available 2025-06), built around three principles:

• Connected: connects engineers, EDA tools, and verification IP across Questa One, Tessent DFT, and Veloce CS.
• Data-Driven: generative, prescriptive, and predictive machine learning.
• Scalable: efficient convergence through acceleration and automation.

On this basis Siemens launched the Questa One Agentic Toolkit, embedding domain-specific AI agents within Questa One, covering the full pipeline of "planning → RTL creation → debugging → sign-off". Its Harness characteristics are worth recording one by one:

1. L2 interface standardization: built on NVIDIA Llama Nemotron and NVIDIA NIM, provides MCP (Model Context Protocol), exposing verification state to agent frameworks through a standardized interface.
2. Engine-native intelligence: agents hook into existing simulation engines rather than replacing them.
3. Framework-agnostic: not bound to any specific agent framework.
4. L3 governance boundary: reasons, plans, and executes autonomously within customer-defined governance boundaries, retaining configurable human supervision at key decision points.

3.1.3. Results

Siemens' officially released quantified results:

• Coverage Acceleration: reaches coverage targets 50x faster than traditional testbench solvers.
• DFT Simulation Acceleration: gate-level serial pattern simulation 8x acceleration (combining parallel simulation with Tessent SSN).
• Fault Simulation Acceleration: 48x (supports functional-safety and DFT fault simulation, and supports Tessent UDFM).
• Stimulus Free Verification: processing time of a complex open-source SoC-level reference design reduced from over 24 hours to under 1 minute; integrates 20 stimulus-free analyses, including automatic lint fixes and automated SVA generation and verification.
• Questa One Avery VIP: protocol-aware debugging and coverage analysis; the same CTS, testbench, and stimulus can be reused on Veloce CS emulation and prototyping systems.

3.2. Cadence ChipStack Large-Scale Acceleration on the Verification Side

Evidence level: A (Cadence official press release)

3.2.1. Background

Verification is the earliest scenario where ChipStack landed. Cadence acquired AI2-incubated ChipStack in 2025-11, released the ChipStack AI Super Agent on 2026-02-10, and early customers include NVIDIA, Altera, Qualcomm, and Tenstorrent.

3.2.2. Solution

ChipStack orchestrates multiple "virtual engineers", all calling Cadence's underlying EDA tools and built on the sign-off-accuracy results of Xcelium (dynamic simulation) and Jasper (formal verification). Technical highlights:

• Automated formal test-plan generation: derives the verification plan from design intent combined with Mental Models.
• Dual-engine combination of dynamic simulation and formal verification: simulation provides coverage signals; formal verification provides exhaustive proof.
• Sandbox governance: runs within the NVIDIA OpenShell sandbox runtime, providing policy control, isolation, and controlled access to tools and design data.
• Announced expansion to Level-5 full autonomy at Computex on 2026-06-01, natively compatible with Codex and Claude Code.

3.2.3. Results

• NVIDIA internally: each engineer runs hundreds of Xcelium dynamic simulations + Jasper formal verifications with ChipStack, with the RTL verification cycle accelerated by 40x or more and the typical 5-week verification loop cut to under 1 day.
• Altera (Arvind Vidyarthi, Senior Director of Engineering): verification workload reduced by ~10x in some areas, achieving deeper functional coverage on the most complex designs.
• Tenstorrent (Daniel Cummings, Principal Engineer of RISC-V cores): across 3 key design modules over a 3-month evaluation, formal verification time cut by up to 4x.

Significance to this direction: the 40x figure was achieved not by a "smarter model" but by "automating engine invocation + automating test-plan generation + automating the debug loop". It validates a judgment: in the verification direction, the engineering value of the Harness is greater than the intelligence value of the model itself.

3.3. 芯华章 and 中兴微电子: LLM Auto-Generation of SVA Assertions

Evidence level: C (compilation from long-form Chinese technical community articles)

3.3.1. Background

Handwriting SVA assertions easily misses boundary scenarios; complex assertions (such as "the target signal matches within 10 cycles after a signal change" and "asynchronous clock domain assertion synchronization") have long debug cycles and depend heavily on engineer experience.

3.3.2. Solution

An SVA generation system based on large language models, adopting the closed-loop structure of iterative prompt optimization + metric evaluation (SVAEval). The system can automatically generate assertion code containing temporary variables, time windows, and cross-clock-domain handling.

3.3.3. Results

According to the compilation from long-form Chinese technical community articles (Level C):

• Covers 20%+ of the boundary scenarios that traditional handwriting easily misses.
• Complex assertions see development efficiency improved by 40%+.
• The original 3-day debug cycle is reduced to hours.

Related research: Peng Li and Wang Ding of MetaX (沐曦集成电路) published "DeepSeek Accelerates GPU Chip Verification Coverage Closure Technology" in the 2025 issue of Integrated Circuit Applications (《集成电路应用》).

Mandatory warning: none of this case's quantified figures has been confirmed by a first-hand source. Its value as a technical roadmap reference (iterative prompt optimization + metric evaluation loop) is higher than the value of its quantified results. When citing, the nature of the source must be noted, and it must not be used as the sole basis for decisions.

4. Practice Standards

Nature statement: the following AGENTS.md and SKILL.md are advisory drafts distilled from public industry practice, not the text of any official industry standard. As of the writing of this document, no public AGENTS.md or SKILL.md standard template targeting the chip verification direction has been found.

4.1. AGENTS.md Specification

4.1.1. AGENTS.md (Chip Verification)

# AGENTS.md —— 芯片验证

> 本文为基于行业实践提炼的建议稿，非官方行业标准原文。

## 角色与边界
- 角色：芯片验证智能体，负责测试计划生成、UVM 平台构建、SVA 断言生成、
  覆盖率收敛、形式验证辅助与缺陷定位。
- 挂钩引擎，不替换引擎：所有覆盖率、证明、pass/fail 结论必须由 Xcelium / Jasper /
  Questa One / VCS / Verilator 等真实工具给出。
- 自主性边界：在客户定义的治理边界内自主推理-规划-执行；关键决策点保留可配置人工监督。
- 不负责：签核放行签字、覆盖率模型的最终削减决定、流片放行。

## 环境假设
执行前必须显式声明：
- 仿真器及版本（Xcelium / Questa / VCS / Icarus Verilog / Verilator）。
- 形式验证引擎及版本（Jasper / VC Formal / Questa Formal）。
- UVM 版本（IEEE 1800.2-2020，参考实现 UVM 2020-2.0）与 SystemVerilog 版本（IEEE 1800-2023）。
- 覆盖率互操作格式（Accellera UCIS 1.0）与覆盖率数据库路径。
- 可移植激励标准支持情况（Accellera Portable Stimulus 2.0）。
- 断言库（Accellera OVL 2.8.1）与协同仿真接口（Accellera SCE-MI 2.3）。
- 回归农场并发上限、EDA 授权配额、磁盘配额。
- 车规场景须声明目标 ASIL 等级与 ISO 26262-11:2018 适用条款。

## 上下文加载顺序（Context Budget）
1. 设计规范相关章节与验证计划（测试意图、覆盖点定义）。
2. 覆盖率模型定义与当前覆盖率数据库摘要。
3. 失败用例列表、波形索引、历史根因分析。
4. 项目编码规范与 UVM 平台约定。
5. 保持"设计、testbench、测试计划、规范"四者之间的上下文关联，不得只加载其一。
- 完整波形、大规模回归日志不进上下文，以路径引用 + 工具查询代替；
  查看波形时只提取指定时间窗与指定信号。

## 工具契约
- 优先为仿真器与形式引擎封装 MCP 服务器，通过标准化接口访问验证状态。
- 工具返回值必须包含：退出码、日志路径、覆盖率数值、随机种子、工具版本。
- 同一任务在相同种子下必须可复现；所有调用须记录完整命令行或脚本。
- 并发回归不得超过声明的 CPU 与授权配额。
- 覆盖率数据跨工具合并时，须通过 Accellera UCIS 1.0 或等效互操作格式。

## 任务执行流程（SOP）
- S1 需求解析：把验证目标分解为可判定的覆盖点与属性。
- S2 基线建立：跑基线回归，记录覆盖率、种子、运行时长、CPU 消耗。
- S3 候选生成：产出候选激励策略、断言、测试计划条目，每个附理由与预期影响。
- S4 引擎判定：调用仿真与形式引擎，得到客观覆盖率与证明结果。
- S5 差异分析：与基线对比；识别假收敛与不可达覆盖仓。
- S6 回归压缩：在覆盖率不回退的前提下压缩测试集，并验证诊断能力未丢失。
- S7 证据打包：命令、脚本、日志路径、覆盖率数值、种子、版本齐备。
- S8 人工确认：覆盖率模型的变更与签核放行进入人工审批队列。

## 验证与证据要求
- 覆盖率目标不可由"生成更多测试"凑数：必须区分代码覆盖率与功能覆盖率，
  识别不可达覆盖仓（UNR），否则会出现"覆盖率 100% 但仍有设计漏洞"的假收敛。
- 断言（SVA）必须由形式化工具验证，不能只靠 LLM 生成即通过。
- 形式验证结论须附证明状态（proven / vacuous / bounded / inconclusive），
  不得把 vacuous（空证明）当作通过。
- 唯一缺陷发现数为必需指标：本轮相对基线新发现了多少此前未发现的缺陷。
- 测试压缩必须同时报告：压缩倍数、覆盖率变化、DPPM 或客户逃逸率是否恶化。
- 每条结论须附：工具名 + 版本 + 命令或脚本 + 日志路径 + 关键数值 + 随机种子。

## 失败与升级策略
- 连续 3 轮迭代覆盖率无增长 → 升级人工，并输出未覆盖点根因分析（RCA）。
- 出现 vacuous proof（空证明）或证明不收敛 → 升级人工复核属性与约束。
- 测试压缩后诊断能力下降或 DPPM 恶化 → 立即回滚至上一基线。
- 仿真器报未知错误或授权失败 → 停止执行，不得绕过授权重试或改参数强行绕过。
- 升级时须交付：已完成证据包 + 失败点定位 + 下一步可执行的具体命令。

## 安全与合规红线
- 自主智能体必须在沙箱运行时内执行（参考 NVIDIA OpenShell：策略控制、隔离、
  对工具/基础设施/设计数据的受控访问）。
- 设计、testbench、覆盖率数据库、缺陷库属企业核心 IP，不得离开企业网络边界。
- 车规场景须符合 ISO 26262-11:2018：安全机制诊断覆盖率、故障注入、FMEDA、
  SPFM / LFM / PMHF 三项硬件架构度量、软错误（SEU / SET / MBU）分析。
- 覆盖率模型的任何削减必须有书面理由与批准记录，禁止为达标而删除覆盖点。
- 所有工具调用、覆盖率模型变更、人工确认写入不可篡改审计日志。

## 禁止事项
- 禁止编造或臆测覆盖率数值、证明结果、缺陷定位结论。
- 禁止输出"应该没问题""大概率通过"等不可判定表述。
- 禁止把 vacuous proof 记为通过。
- 禁止为达成覆盖率目标而放宽覆盖率模型、删除覆盖点或缩小测试范围。
- 禁止绕过形式化验证直接采纳 LLM 生成的断言。
- 禁止把设计、testbench、良率或缺陷数据上传至未授权外部服务。
- 禁止虚构标准编号；未确认标准一律标注 [待核实]。
- 禁止在无人确认下触发签核放行等不可逆动作。

## 输出格式
- 首行给出可判定结论（通过 / 不通过 / 部分通过 + 阻塞项）。
- 证据表：工具、版本、命令或脚本、日志路径、覆盖率数值、种子、与基线差值。
- 覆盖率分项：代码覆盖率与功能覆盖率分别列出，并单列不可达覆盖仓数量。
- 缺陷清单：唯一缺陷发现数、缺陷严重度、定位证据。
- 风险与假设：列出结论依赖的种子、覆盖率模型版本、约束前提。
- 待人工确认项：覆盖率模型变更、签核放行、缺陷责任归属。
- 数值规范：参数带单位；范围用 ~ 连接；百分比数值与 % 之间不留空格。

## 评估与自检
- 本轮覆盖率数值是否全部来自真实工具输出？
- 代码覆盖率与功能覆盖率是否已分别报告？不可达覆盖仓是否已识别？
- 是否存在 vacuous proof？是否已被排除在通过项之外？
- 唯一缺陷发现数是多少？是否只是重复命中既有覆盖？
- 测试压缩是否导致诊断能力下降？DPPM 是否恶化？
- 覆盖率模型是否发生过未经批准的变更？
- 结论依赖的种子与工具版本是否已记录？
- 输出中是否残留 XX、___ 等非标准占位符？
- Harness 或提示词变更后，是否在固定黄金回归集上回归并报告与上一版本的差值？

4.2. SKILL.md Specification

4.2.1. SKILL.md (Chip Verification · Coverage Closure and Assertion Generation)

---
name: chip-verification-coverage-closure
description: 芯片验证方向的覆盖率收敛与断言生成技能。当需要分析覆盖率空洞、偏置激励、
  压缩回归集、生成并验证 SVA 断言、做形式化证明，并要求覆盖率真实增长且不出现假收敛时使用。
version: 1.0
created: 2026-09-12
---

# 芯片验证 · 覆盖率收敛与断言生成

> 本文为基于行业实践提炼的建议稿，非官方行业标准原文。

## 适用场景
- 功能覆盖率长期停滞在某一水平，需要定位空洞并制定收敛策略。
- 回归集规模膨胀导致周转时间（TAT）过长，需要在不回退覆盖率的前提下压缩。
- 依据规范与设计意图生成 SVA 断言，并用形式化工具验证。
- 模块级或数据通路的形式化完备证明。
- 回归失败用例的自动定位与根因分析。
- 车规场景下的安全机制诊断覆盖率评估与故障注入验证。

## 前置条件
- 已声明仿真器、形式验证引擎、UVM 版本、覆盖率互操作格式。
- 存在可重跑的基线回归（固定种子与脚本版本）与覆盖率数据库。
- 覆盖率模型已定义并冻结版本；变更需走审批。
- 智能体运行于隔离运行时，工具与数据访问受策略控制。
- 具备判定器：仿真 pass/fail、覆盖率数值、形式证明状态。
- 回归农场的并发与授权配额已明确。

## 输入
| 输入项 | 说明 | 必需 |
|---|---|---|
| 验证计划 | 测试意图、覆盖点定义、优先级 | 是 |
| 设计规范 | 相关章节与接口行为约定 | 是 |
| 设计源文件 | RTL、UVM testbench、约束、覆盖率模型 | 是 |
| 基线覆盖率报告 | 代码覆盖率、功能覆盖率、不可达覆盖仓 | 是 |
| 回归配置 | 种子策略、并发数、TAT 目标 | 是 |
| 环境清单 | 仿真器与形式引擎版本 | 是 |
| 失败用例 | 上轮回归失败列表与日志路径 | 否 |

## 输出
| 输出项 | 说明 | 必需 |
|---|---|---|
| 可判定结论 | 通过 / 不通过 / 部分通过 + 阻塞项 | 是 |
| 覆盖率分项表 | 代码覆盖率与功能覆盖率分别列出，含与基线差值 | 是 |
| 不可达覆盖仓清单 | 识别出的 UNR 数量与判定依据 | 是 |
| 断言清单 | 生成断言条目、形式验证状态、vacuous 检查结果 | 是 |
| 唯一缺陷清单 | 本轮新发现缺陷数、严重度、定位证据 | 是 |
| 回归压缩报告 | 压缩倍数、覆盖率变化、诊断能力影响 | 条件必需 |
| 证据表 | 工具、版本、命令或脚本、日志路径、数值、种子 | 是 |
| 待人工确认项 | 覆盖率模型变更、签核放行 | 是 |

## 执行步骤
1. 环境校验：核对仿真器、形式引擎、UVM 与覆盖率格式版本；缺失即停止。
2. 基线重跑：固定种子重跑基线回归，记录覆盖率、TAT、CPU 消耗。
3. 空洞分析：分析未命中覆盖点，区分"可达未命中"与"不可达"。
4. 候选生成：产出候选动作 —— 偏置激励至未命中覆盖仓、补充 SVA 断言、
   生成定向测试、排除不可达覆盖仓。
5. 引擎判定：执行仿真与形式验证，记录命令、退出码、日志路径、种子。
6. 断言验证：所有生成断言送形式化工具验证，逐条检查是否存在空证明。
7. 回归压缩：在覆盖率不回退前提下压缩测试集，并验证诊断能力未丢失。
8. 差异分析：与基线对比，改善项与恶化项同时报告。
9. 证据打包与交付：列出待人工确认项，写入审计日志。

## 质量标准（DoD）
- 覆盖率数值全部来自真实工具输出，且代码覆盖率与功能覆盖率分别报告。
- 不可达覆盖仓已识别并有判定依据，不得靠"生成更多测试"掩盖。
- 所有生成断言经形式化工具验证，无 vacuous proof 被记为通过。
- 唯一缺陷发现数已统计并附定位证据。
- 回归压缩后覆盖率不回退，诊断能力未丢失。
- 形式证明结论附状态标记（proven / vacuous / bounded / inconclusive）。
- 每条结论附工具名 + 版本 + 命令或脚本 + 日志路径 + 关键数值 + 随机种子。
- 覆盖率模型无未经批准的变更。
- 输出中无 XX、___ 等非标准占位符；未确定项统一标注 [待填写] 或 [待核实]。
- 参考阈值：Siemens Questa One 官方口径为覆盖加速 50 倍、DFT 仿真加速 8 倍、
  故障仿真加速 48 倍、无激励验证 24h+ 降至 1min 以内（级别 A）；
  Cadence ChipStack 在 NVIDIA 内部实现验证周期提速 40 倍以上（级别 A）。
  这些为厂商口径，项目内应建立自己的基线与目标。

## 常见失败与处理
| 失败模式 | 现象 | 处理 |
|---|---|---|
| 假收敛 | 覆盖率达标但设计仍有漏洞 | 拆分代码与功能覆盖率，补充形式证明，复核覆盖点定义 |
| 空证明 | 断言被证明但因前提不可达而恒真 | 逐条做 vacuous 检查，空证明不计入通过 |
| 不可达覆盖仓 | 求解器在死胡同浪费算力 | 识别并排除 UNR，记录判定依据 |
| 回归膨胀 | 测试集越跑越大，TAT 不可控 | 智能压缩并验证诊断能力，DPPM 恶化即回滚 |
| 激励偏置失控 | 覆盖率上升但随机性丧失 | 压缩同时保留随机性，报告种子多样性 |
| 断言幻觉 | LLM 生成语法正确但语义错误的断言 | 强制形式化验证，未通过不采纳 |
| 工具特异性差异 | 同一 testbench 不同仿真器结果不同 | 固定工具与版本，证据表显式标注 |
| 无限循环 | 反复重生成无收敛 | 重试上限 3 轮，超限升级人工 |

## 示例
任务：某模块功能覆盖率长期卡在 92%，需在两周内收敛至签核目标，且不得恶化 DPPM。
1. 环境校验：确认仿真器版本、UVM 版本（IEEE 1800.2-2020）、覆盖率模型路径、并发配额。
2. 基线重跑：固定 3 个种子重跑基线，记录代码覆盖率、功能覆盖率、TAT。
3. 空洞分析：定位未命中覆盖点，区分可达未命中与不可达。
4. 候选生成：三类动作 —— 偏置激励至未命中覆盖仓、补充 SVA 断言、排除不可达覆盖仓。
5. 引擎判定：分别执行，记录种子、日志路径、覆盖率变化、CPU 时长。
6. 断言验证：新增 24 条断言，21 条形式验证通过，3 条被证伪并定位到真实设计缺陷。
7. 回归压缩：在覆盖率不回退前提下压缩，验证诊断能力未丢失。
8. 差异分析：功能覆盖率提升至 96.8%，CPU 时长 +12%，识别不可达覆盖仓 137 个。
9. 交付：结论"部分通过，签核目标达成，遗留 1 个阻塞项（3 条被证伪断言对应的设计缺陷
   需设计方确认）"；证据表含工具版本、命令、日志路径、种子、与基线差值。

## 关联
- 与设计方向的边界：设计与验证在 Agentic 架构下已不分离；ChipStack 的 40 倍提速
  正是 Xcelium 动态仿真 + Jasper 形式验证组合跑出来的。
- 与测试方向的边界：验证面向设计正确性（pre-silicon），测试面向制造缺陷（post-silicon）；
  两者在故障仿真环节合流，IEEE 1838 的 3D DFT 架构依赖 IEEE 1687 IJTAG 与 IEEE 1500 wrapper。

4.3. Implementation Checklist

5. Summary

Chip verification is the direction in which the six-layer model's L5 evaluation and observation layer is strongest and landed earliest. The fundamental reason is not that the model is smarter, but that the verification stage naturally possesses every element reinforcement learning needs: coverage is a ready-made reward function, the simulator is a ready-made judge, and the regression farm is a ready-made sample generator. This structural advantage makes "the engineering value of the Harness greater than the intelligence value of the model itself" most evident in this direction — ChipStack's 40x speedup at NVIDIA came from the automation of engine invocation, test-plan generation, and the debug loop, not a leap in model capability.

The direction's three non-negotiable items:

1. Zero tolerance for false convergence. Coverage must distinguish code coverage from functional coverage, and unreachable cover bins must be identified and excluded. A 100% coverage padded out by "generating more tests" is a negative asset.
2. Assertions must be proven. LLM-generated SVA assertions must be verified by formal tools, and each one must be checked for a vacuous proof — a vacuous proof is "pass" numerically but "nothing verified" semantically.
3. Compression must not sacrifice diagnostic capability. The benefits of test compression must be jointly evaluated against DPPM, customer escape rate, and fault coverage; any degradation means rollback.

Finally, an industry-level gap must be noted: no public EDA Agent benchmark covering the full workflow of "tool invocation + multi-round debugging + coverage closure" has been found. The existing VerilogEval, CVDP, and RealBench only evaluate RTL generation capability. This means the direction currently cannot horizontally compare different Harness implementations and can only rely on enterprises' internal private regression sets. This is a real and important open challenge.

Information Gap Statement

The following items have not been confirmed by Level-A or Level-B sources and are marked [To be verified] in the main text:

1. Verification team size is 2~5 times the RTL design team (Level C).
2. Roughly 70% of compute in traditional UVM random stimulus is spent on redundant tests (Level C).
3. All Synopsys VSO.ai customer quantified figures: OpenTitan HMAC IP 3x, Renesas 10x and +30%, AMD 1.5~16x and TAT 16x, NVIDIA +33% and 5x and 3.5x and 4 unique bugs, Microsoft 300 seeds, Cisco +9% (Level C).
4. Cadence Verisium SimAI Qualcomm measured figures: seed compression 4~5x, GPU team 2x efficiency, fabric bus close-loop time reduced 30% (Level C).
5. Cadence Verisium L1-level 2026 statement: project turnaround 5~10x, coverage convergence 2x, regression compression 2~7x (Level C).
6. 芯华章 and 中兴微电子 SVA generation: +40% efficiency, 20%+ boundary scenarios, 3 days reduced to a few hours (Level C).
7. 芯华章 GalaxSim Turbo 3.0 >10x improvement and GalaxEC-HEC saving 9x manpower (Level C).
8. EDA National Innovation Center ChatDV's four-module capability description: iModel / iSVA / iTest / iDebug (Level C).
9. Cadence's estimated shortfall of several hundred thousand chip design and verification engineers by 2030 (Level C).
10. IEEE 1850-2010 (PSL) status is Inactive - Reserved; cite it noting its dormant status. The exact release years of Accellera's current standards (Portable Stimulus 2.0, UCIS 1.0, OVL 2.8.1, SCE-MI 2.3) have not been confirmed, so this document does not state years.
11. No public EDA Agent benchmark covering the full workflow has been found; proposed as an open challenge in Section 5.

6. References

1. Siemens Questa One Redefines IC Verification for Complex Chips — ENGtechnica, 2025. https://engtechnica.com/siemens-questa-one-redefines-ic-verification-for-complex-chips
2. Siemens official interview (Questa One Agentic Toolkit and MCP architecture). https://plm-erpnews.se?p=35639/
3. Cadence Unveils Industry's First Fully Autonomous Virtual Engineer — Cadence, 2026. https://www.cadence.com/ja_JP/home/company/newsroom/press-releases/pr/2026/cadence-unveils-industrys-first-fully-autonomous-virtual.html
4. Cadence Extends Chip Design Agent to Level 5 Autonomy — engineering.com, 2026. https://www.engineering.com/cadence-extends-chip-design-agent-to-level-5-autonomy/
5. Accellera Federated Simulation Standard PWG introduction (including the current standard list of UVM, UCIS, OVL, SCE-MI, Portable Stimulus) — Accellera, 2023. https://accellera.org/images/activities/Federated-Simulation-Standard-PWG-intro.pdf
6. IEEE 1800-2023 SystemVerilog — Design And Reuse / IEEE joint page. https://us.design-reuse.com/exit/?urlid=9987
7. ISO 26262-11:2018 Road vehicles — Functional safety — Part 11 — ISO. https://www.iso.org/fr/contents/data/standard/06/96/69604.html
8. What Are Agentic AI RTL Verification Tools and How Are They Changing Chip Design Workflows in 2026 — designedbyai.io. https://designedbyai.io/knowledge/what_are_agentic_ai_rtl_verification_tools_and_how_are_they_changing_chip_design_workflows_in_2026.php
9. Real-World Chip Design Workflows: Technical Overview — BITSILICA. https://www.blogarama.com/technology-blogs/1445797-BITSILICA-Pvt-Ltd-Blog/70164062-real-world-chip-design-workflows-technical-overview
10. IEEE 1838 Explained: How DFT Evolves for 2.5D, 3D and 3.5D ICs — LoveChip. https://www.lovechip.com/blog/ieee-1838-explained-how-dft-evolves-for-2-5d-3d-and-3-5d-ics
11. VerilogEval v2 — ACM Transactions on Design Automation of Electronic Systems 30(6), 2025-10-21. https://dl.acm.org/doi/abs/10.1145/3718088
12. 3D IC / Chiplet DFT engineering practice — 3D InCites. https://www.3dincites.com/?p=76406
13. Accellera official website (standard downloads and open-source UVM implementation). https://accellera.org/
14. IEEE Xplore DASC survey (IEEE Get program's free standard list). https://ieeexplore.ieee.org/document/9473237/keywords