硬件研发组
1. 介绍
1.1. 组的定位
硬件研发组覆盖芯片从架构定义到量产交付的完整链路，划分为五个方向：芯片设计（01）、芯片验证（02）、封装（03）、测试（04）、AI Infra（05）。
在 AI Harness 体系中，本组是最能检验"Harness 是否真的把模型的不确定性转化为工程可预期性"的试金石。原因在于硬件域同时具备两个极端特征：
- 反馈闭环最贵：一次先进节点 tape-out 的代价以亿美元计（IBS 估计 5nm~3nm 单颗 2 亿~5 亿美元以上，证据级别 B），设计错误无法像软件那样热修复。
- ground truth 最硬：仿真器、形式验证引擎、ATE 测试机、量测设备都能给出确定性的通过或失败判定。模型不需要"自我评估"它做得对不对，工程工具链会直接告诉它。
正因为第 2 点，AI Harness 的 L5 评估与观测层在硬件域不是"额外搭建"的，而是天然存在的既有基础设施：覆盖率数据库、回归农场、形式验证证明、晶圆量测数据，都是成熟的判定器。Agentic AI 在 EDA 领域最早的规模化落地集中在验证、调试、覆盖率收敛，而非综合或布局布线，根本原因就是这些环节已经具备高频、可判定、低成本的反馈闭环。
图 1-1｜硬件研发组在 AI Harness 六层模型中的定位
数据来源：基于本文分析绘制的示意图。
1.2. 本组的核心论断
论断一：硬件研发组是六层模型中 L2（工具与执行）与 L5（评估与观测）最重的一组。
- L2 层面，EDA 工具不可替代。智能体的正确姿势不是"取代引擎"，而是"编排引擎"。Cadence ChipStack 在 NVIDIA OpenShell 沙箱内编排 Xcelium（动态仿真）与 Jasper（形式验证）；Siemens 自建 MCP（Model Context Protocol）服务器把 Questa One 引擎能力暴露给智能体框架，并明确强调"挂钩现有仿真引擎而非替换它们"。这两者都是 L2 的现成范式。
- L5 层面，形式化验证与逻辑等价性检查（LEC）是唯一可判定的 ground truth。任何 AI 优化后的网表，必须与黄金 RTL 做形式等价性检查，确认功能行为未改变，才可进入后续流程。
论断二：硬件研发组是 L6（治理与安全）代价最高的一组。
软件缺陷可以打补丁，芯片 tape-out 不可逆。因此本域的 Harness 必须是"人类在环 + 强沙箱 + 强审计"，而非全自动。NVIDIA OpenShell 沙箱运行时是当前最直接的现成范式：它为自主智能体提供策略控制、隔离、以及对工具、基础设施、设计数据的受控访问，以保护机密 IP。CADENCE ChipStack 的 Level-5 全自主能力即运行于其中。
论断三：EDA 领域的公开基准与真实生产力之间存在显著落差，评估设计必须防作弊。
VerilogEval v2 上 GPT-4o 的 spec-to-RTL pass@1 为 63%；但据公开演讲整理，更贴近生产环境的 CVDP 基准上成绩降至 10%~40%，最难的 RealBench 至今无 AI 系统解出任何一题（证据级别 C）。因此本组所有 AGENTS.md 与 SKILL.md 均要求：禁止只报学术基准成绩，必须同时报告项目内真实回归指标。
1.3. 行业图景数据
| 维度 | 数据 | 来源性质 |
|---|---|---|
| RTL 验证占项目周期比例 | 60%~70%（复杂 SoC） | 行业综述，级别 B |
| 验证团队规模相对 RTL 设计团队 | 2~5 倍 | 中文技术社区长文，级别 C， |
| AI 赋能 EDA 的潜在设计成本节省 | 20%~30%（Semico Research 预测）；14nm SoC 代表性实测 21.3% | 汇编资料，级别 B |
| 行业在 AI 设计工具上的支出 | 2023 年 3 亿美元，年增 20%，2026 年超 5 亿美元（Deloitte TMT Predictions） | 汇编资料，级别 B |
| 先进封装市场规模 | 2029 年 695 亿美元，将首次超过传统封装（SEMI 中国 / HIIC 2025） | 官方纪要，级别 A- |
| IC 封装组装市场规模 | 2024 年 610 亿美元 → 2029 年 880 亿美元（Prismark 合伙人，HIIC 2025） | 官方纪要，级别 A- |
| 全球半导体市场 | 2024 年 6,280 亿美元 → 2029 年 9,080 亿美元，CAGR 7.7% | 官方纪要，级别 A- |
| 先进节点单颗 tape-out 成本 | 5nm~3nm 为 2 亿~5 亿美元以上（IBS 估计） | 汇编资料，级别 B |
需要特别说明的是：本表中标注 的数字来自二手中文转载，未获一手来源确认，引用时应同时标注来源性质，不得作为决策的唯一依据。
2. 名词解释
| 术语 | 英文 / 缩写 | 释义 |
|---|---|---|
| 电子设计自动化 | Electronic Design Automation，EDA | 用于集成电路设计、仿真、验证、物理实现的工具链总称 |
| 寄存器传输级 | Register Transfer Level，RTL | 以寄存器与寄存器间组合逻辑描述电路行为的设计抽象层级 |
| 功耗、性能、面积 | Power, Performance, Area，PPA | 衡量芯片实现质量的三大指标，三者通常相互制约 |
| 流片 | Tape-out | 将最终版图数据交付代工厂制造的关键节点，此后设计变更成本极高 |
| 逻辑等价性检查 | Logic Equivalence Checking，LEC | 用形式化方法证明优化前后网表与黄金 RTL 功能等价 |
| 通用验证方法学 | Universal Verification Methodology，UVM | 基于 SystemVerilog 的标准化验证平台方法学，IEEE 1800.2-2020 |
| 形式验证 | Formal Verification | 用数学方法穷尽证明设计满足给定属性，不依赖测试向量 |
| 断言 | SystemVerilog Assertion，SVA | 以时序逻辑描述设计应满足的属性，是形式验证与仿真的共同输入 |
| 覆盖率收敛 | Coverage Closure | 通过补充激励与断言，使功能覆盖率与代码覆盖率达到签核目标的过程 |
| 可测性设计 | Design for Test，DFT | 在设计中插入扫描链、压缩结构、内建自测试等以提升可测性的方法 |
| 自动测试设备 | Automated Test Equipment，ATE | 对芯片施加测试向量并判定合格与否的量产测试机台 |
| 已知良好裸片 | Known Good Die，KGD | 已完成晶圆级测试并判定为良品的裸片，是 Chiplet 堆叠的前提 |
| 通用芯粒互连标准 | Universal Chiplet Interconnect Express，UCIe | Die-to-Die 互连的开放标准，当前版本 3.0（2025-08-05 发布） |
| 高带宽存储 | High Bandwidth Memory，HBM | 通过 TSV 垂直堆叠与超宽总线实现高带宽的存储器，JEDEC JESD235 / JESD238 / JESD270-4 系列 |
| 硅中介层 | Silicon Interposer | 2.5D 封装中承载多裸片高密度互连的硅基板，如 CoWoS-S |
| 模型上下文协议 | Model Context Protocol，MCP | 把外部工具与数据源以标准接口暴露给智能体的开放协议 |
| 模型算力利用率 | Model FLOPs Utilization，MFU | 实际有效算力与理论峰值算力之比，是训练集群的核心效率指标 |
| 有效训练时间比率 | Effective Training Time Ratio，ETTR | 有效训练时间占总占用时间的比例，反映容错与故障恢复能力 |
| 电源使用效率 | Power Usage Effectiveness，PUE | 数据中心总能耗与 IT 设备能耗之比，越接近 1 越优 |
| 每百万缺陷器件数 | Defective Parts Per Million，DPPM | 出厂产品中的缺陷器件比例，是测试压缩不可逾越的底线指标 |
3. 五个方向的定位对比
3.1. 方向总览对比表
| 方向 | 主要任务 | 核心执行器 | 判定的 ground truth | 主要风险 | 典型量化收益（证据级别） |
|---|---|---|---|---|---|
| 01 芯片设计 | RTL 生成、架构探索、综合、布局布线、PPA 优化 | Design Compiler / Fusion Compiler / Innovus / Yosys / Cerebrus / DSO.ai | LEC 形式等价检查 + 时序签核 + 综合通过率 | 网表功能被改变；代理指标（近似线长、拥塞）与最终真实性能脱节 | Cerebrus 最高 10 倍生产力 + 20% PPA（A）；ChipStack 前端设计验证最高 10 倍（A） |
| 02 芯片验证 | UVM 平台、SVA、覆盖率收敛、形式验证、缺陷定位 | Xcelium / Jasper / Questa One / VCS / Verisium | 覆盖率 + 形式证明 + 回归 pass/fail | 假收敛：覆盖率 100% 仍有设计漏洞；不可达 bin 造成算力浪费 | Questa One 覆盖加速 50 倍（A）；ChipStack 在 NVIDIA 内部验证周期提速 40 倍以上（A） |
| 03 封装 | 2.5D/3D 集成、Chiplet 互连、信号/电源完整性、热与应力协同 | 3DIC Compiler / RedHawk-SC / Icepak / Ansys 多物理场 / 芯和半导体平台 | DRC/LVS + 热-力-电签核 + UCIe 一致性测试 | 多厂商 IP 边界不清；Die-to-Die 协议丛林；热-力-电耦合失配 | UCIe 3.0 达 48/64 GT/s（A）；Synopsys 与 Ansys 合并后聚焦多裸片先进封装（A） |
| 04 测试 | ATE 程序、DFT 插入、自适应测试、良率分析、失效分析 | ATE 平台（Advantest / Teradyne）、Tessent / TestMAX、诊断工具 | DPPM、客户逃逸率、良率、故障覆盖率 | 测试压缩导致诊断能力丢失；模型跨工艺节点泛化性不足 | ACS RTDI 早期试点延迟降低最高 30%、测试预算节省超 15%（A） |
| 05 AI Infra | 算力集群、训练与推理平台、调度、互联、能耗 | 作业调度器、监控系统、固件工具、MGX 参考设计 | MFU、ETTR、有效训练时长占比、PUE | 训练中断频繁；故障恢复慢；能耗与配额失控 | GB200 NVL72 液冷使成本与能耗降低 25 倍（A）；夸娥万卡集群 Dense 模型 MFU 60%（B，厂商口径） |
3.2. 五方向与 Harness 六层映射表
| 方向 | L1 上下文工程 | L2 工具与执行 | L3 编排与控制 | L4 记忆与状态 | L5 评估与观测 | L6 治理与安全 |
|---|---|---|---|---|---|---|
| 01 芯片设计 | 设计规范、PPA 历史库、工艺设计包 | 综合与布局布线工具（Yosys / Design Compiler / Fusion Compiler / Innovus） | 架构探索 DAG、参数空间搜索 | warm-start 迁移学习（DSO.ai 复用先前设计知识） | PPA 指标 + 形式等价检查 | IP 隔离、OpenShell 沙箱、IEEE 1735-2023 |
| 02 芯片验证 | 规范、测试计划、覆盖率模型、回归日志 | 仿真器 + 形式引擎（Xcelium / Jasper / Questa One / VCS） | 回归编排、智能体多步工作流 | 历史回归数据库、覆盖率数据库 | 覆盖率 + 形式验证（最强 ground truth） | 签核留痕、人工在环、治理边界内自主 |
| 03 封装 | 多物理场模型、工艺设计包、Chiplet 元数据 | SI/PI/热/应力仿真器（RedHawk-SC / Icepak / 3DIC Compiler） | 系统技术协同优化（STCO） | 工艺与良率知识库 | DRC/LVS + 热-力-电签核 | 多厂商 IP 边界（UCIe / IP-XACT） |
| 04 测试 | 晶圆图、ATE 日志、失效样本库 | ATE 程序、探针台、诊断工具 | 自适应测试流程、实时数据基础设施 | 历史良率与缺陷数据 | DPPM + 客户逃逸率 + 良率 | 车规 ISO 26262-11:2018、数据不出厂 |
| 05 AI Infra | 集群拓扑、作业描述、故障知识 | 调度器、监控系统、固件工具 | 训练容错编排、弹性调度 | 故障知识库、检查点 | MFU + ETTR + PUE | 配额、多租户隔离、能耗预算 |
3.3. 各方向的核心瓶颈层
| 方向 | 瓶颈所在层 | 瓶颈表现 |
|---|---|---|
| 01 芯片设计 | L5 评估与观测 | 设计反馈周期长，一次流片需数月才能知道对错；代理指标与真实性能脱节 |
| 02 芯片验证 | L2 工具与执行 | 工具链异构、引擎授权受限；智能体必须能正确驱动商用引擎而非自建仿真 |
| 03 封装 | L1 上下文工程 | 多物理场、多厂商、多标准的异构数据难以统一表达；IP-XACT 元数据不完整 |
| 04 测试 | L6 治理与安全 | 良率数据与测试程序属核心资产，禁止出企业边界；车规场景还有强制合规约束 |
| 05 AI Infra | L3 编排与控制 | 万卡规模下故障成为常态，容错编排与故障隔离决定有效训练时长 |
4. 共性挑战与对策
| 挑战 | 表现 | 对策 |
|---|---|---|
| 反馈闭环昂贵，试错不可承受 | 先进节点 tape-out 成本 2 亿~5 亿美元以上 | 以 EDA 引擎为唯一裁判，模型只产出候选解；所有候选解在进入签核前必须通过形式等价检查 |
| 设计数据即核心 IP | RTL、网表、版图、测试程序、良率数据泄漏风险高 | 私有化部署；智能体运行于沙箱运行时（NVIDIA OpenShell 提供策略控制与受控访问）；按 IEEE 1735-2023 做 IP 加密与管理 |
| 基准落差导致自我评估失真 | 学术基准 63% 与生产基准 10%~40% 并存 | 禁止只报学术基准；必须在项目内回归集上报告真实指标，并同时报告未覆盖点根因分析 |
| 假收敛 | 覆盖率数字达标但设计仍有漏洞 | 区分代码覆盖率与功能覆盖率；识别不可达 bin；断言必须由形式化工具验证，不能只靠生成即通过 |
| 缺乏 EDA Agent 全流程公开基准 | 现有基准只覆盖 RTL 生成，不覆盖工具调用、多轮调试、覆盖率收敛 | 作为开放挑战提出（详见 4.1）；工程侧先自建内部回归集与黄金案例集 |
| 模型跨工艺节点泛化性不足 | 测试与良率模型换节点后失效 | 上线前做漂移监控；模型输出须附置信区间；保留人工复核阈值 |
| 协议与标准碎片化 | Die-to-Die 互连存在多种协议，生态割裂 | 以 UCIe 3.0 与 IEEE 1685-2022 IP-XACT 为锚定标准，其余协议按适配层处理 |
| 不可逆操作的风险 | 流片、签核、量产放行不可回退 | 所有不可逆动作必须人工确认 + 双签；智能体默认无直接触发权限 |
4.1. 开放挑战：EDA Agent 全流程基准缺失
当前公开的硬件相关 AI 基准（VerilogEval、CVDP、RealBench）主要评测 RTL 生成 这一单点能力，其题目规模小（多小于 100 行、单模块），且智能体系统可访问 testbench、仿真器与波形进行自动调试，与单轮模型不具备可比性。
尚未检索到覆盖"工具调用 + 多轮调试 + 覆盖率收敛"全流程的 EDA Agent 公开基准。这是一个真实且重要的行业空白。它对 Harness 建设的直接影响是：本域无法像软件工程域依赖 SWE-bench 那样，用公开基准横向比较不同 Harness 实现的优劣，只能依赖企业内部的私有回归集。
建议行业侧推进的方向：构建以真实项目回归集为底座、以覆盖率和独特缺陷发现数为奖励、以工具调用轨迹为评测对象的基准；同时公开失败案例，避免基准被"刷题"式优化。
5. 标准与规范地图
| 标准编号 | 名称 | 关联方向 |
|---|---|---|
| IEEE 1800-2023 | SystemVerilog 统一硬件设计、规范与验证语言 | 01 / 02 |
| IEEE 1800.2-2020 | UVM 语言参考手册 | 02 |
| IEEE 1685-2022 | IP-XACT：IP 封装、集成与复用的标准结构 | 01 / 03 |
| IEEE 1801-2024 | UPF 统一功耗格式 | 01 |
| IEEE 1666-2023 | SystemC 语言（含 1666-2023/Cor 1-2025） | 01 |
| IEEE 1735-2023 | 电子设计 IP 加密与管理推荐实践 | 01 / L6 |
| IEEE 1076-2019 | VHDL 语言参考手册 | 01 |
| IEEE 1850-2010 | PSL 属性描述语言（状态：Inactive - Reserved） | 02 |
| IEEE 1450.6.1 | 开放压缩接口（OCI） | 04 |
| IEEE 1149.1 | 测试访问端口与边界扫描架构（JTAG，1990 年首发） | 04 |
| IEEE 1149.6 | 高级数字网络边界扫描测试 | 04 |
| IEEE 1500 | 嵌入式核可测性方法 | 04 |
| IEEE 1687 | IJTAG：器件内嵌仪器访问与控制（2014 年发布） | 04 |
| IEEE 1838-2019 | 三维堆叠集成电路测试访问架构 | 03 / 04 |
| UCIe 1.0 / 1.1 / 2.0 / 3.0 | 通用芯粒互连标准（3.0 于 2025-08-05 发布） | 03 |
| JESD235 / JESD238 / JESD270-4 / JESD79-5 | HBM、HBM3、HBM4、DDR5 | 03 / 05 |
| JESD51 系列 | 封装热特性表征方法 | 03 |
| ISO 26262-11:2018 | 道路车辆功能安全 · 第 11 部分：半导体应用指南 | 01 / 02 / 04 |
| ISO 26262-5 / -9 | 硬件级产品开发 / ASIL 导向分析（SPFM、LFM、PMHF） | 04 |
| Accellera 现行标准 | Portable Stimulus 2.0、SystemRDL 2.0、UCIS 1.0、OVL 2.8.1、SCE-MI 2.3、IP Tagging 1.0、Security Annotation for EDI 1.0、SystemC CCI 1.0、SystemC Synthesis 1.4.7、UVM-SystemC 1.0-beta5 | 01 / 02 |
其中 IEEE 1685-2022、IEEE 1800-2023、IEEE 1801-2024、IEEE 1735-2023、IEEE 1666-2023、IEEE 1800.2-2020 等经 Accellera 通过 IEEE Get 计划向社区免费提供，工程落地时可优先采用。
AI Infra 方向的特别说明：本方向未检索到 IEEE / ISO / JEDEC 面向 AI 算力集群的专用标准（HBM、UCIe 等组件级标准除外）。该方向以事实标准与厂商规范为主，包括 NVIDIA MGX 模块化服务器参考设计、第五代 NVLink 与 NVLink-C2C、Quantum-X800 InfiniBand、Spectrum-X800 Ethernet、BlueField-3 DPU、NVIDIA Dynamo 分离式服务编排框架、OAM（OCP Accelerator Module）模组规范等。撰写相关内容时不得虚构标准编号。
6. 文档导航
| 文档 | 内容 | 适用读者 |
|---|---|---|
| AGENTS.md | 硬件研发组级上位规范，定义五个方向共同遵守的角色边界、工具契约、验证要求与安全红线 | 平台架构师、EDA 工具链负责人 |
| SKILL.md | 硬件研发组级标准技能，覆盖 RTL 生成、验证收敛、PPA 优化等通用任务流 | 智能体开发者、EDA 工程师 |
| 芯片设计 | 芯片设计：RTL 生成、架构探索、前端设计、PPA 优化 | 前端设计工程师、物理设计工程师 |
| 芯片验证 | 芯片验证：UVM、形式验证、覆盖率收敛、缺陷定位 | 验证工程师、形式验证工程师 |
| 封装 | 封装：先进封装、Chiplet、2.5D/3D、热-力-电协同 | 封装工程师、SI/PI 工程师 |
| 测试 | 测试：ATE 测试、良率分析、DFT、失效分析 | 测试工程师、良率工程师 |
| AI Infra（设计侧） | AI Infra：算力集群、训练与推理平台、调度、互联、能耗 | 集群运维、平台工程师 |
阅读顺序建议：先读本篇建立五方向全局认知；再读组级 AGENTS.md 与 SKILL.md 了解共同约束；最后按岗位进入对应方向文档。
7. 总结
硬件研发组是 AI Harness 六层模型中 L2 与 L5 最重、L6 代价最高 的一组。EDA 工具作为不可替代的执行器，决定了 Harness 在这一域的形态是"编排既有引擎"而非"自建能力"；形式化验证与逻辑等价性检查作为唯一可判定的 ground truth，决定了 L5 评估层不需要从零搭建，而应直接复用覆盖率数据库、回归农场与形式证明。
同时，tape-out 的不可逆性把 L6 治理推到了最高优先级：人类在环、沙箱运行时、设计数据受控访问（NVIDIA OpenShell 范式）、以及 IEEE 1735-2023 的 IP 加密管理，构成本域 Harness 不可省略的底座。
需要清醒认识的是，本域当前存在两个真实的能力天花板：一是学术基准与生产基准之间的巨大落差，评估体系必须防作弊；二是缺少覆盖全流程的 EDA Agent 公开基准，导致 Harness 实现之间无法横向比较。这两点应作为后续行业协作的重点方向。
信息缺口声明
以下条目未获 A 级或 B 级来源确认，本文档已在正文中标注 ，在此汇总：
- 验证团队规模相对 RTL 设计团队为 2~5 倍（中文技术社区长文，级别 C）。
- IEEE P2851 的现行状态与编号未获官方确认，本组文档不予引用。
- IEC 61508 的具体版次未获官方页面确认，标注 。
- ISO/SAE 21434 未获官方页面确认，标注 。
- IEEE 1149.1、IEEE 1500、IEEE 1687 的具体现行版次未获 IEEE 官网确认，本组文档只写首发或发布年份并标注 。
- UCIe 1.1 的覆盖温域（有资料称 0℃~125℃）未获官方确认，标注 。
- 中国 Chiplet 相关标准（ACC 1.0、CCLL 白皮书）的编号与发布机构未获官方确认，标注 。
- 未检索到任何公开的、面向芯片或硬件研发的 AGENTS.md / SKILL.md 标准范本。本组的 AGENTS.md 与 SKILL.md 均为基于行业实践与厂商官方文档提炼的建议稿，非官方行业标准原文。
- AI Infra 方向未检索到专用国际或国家标准，该方向以事实标准为主，不得虚构标准编号。
- 未检索到覆盖"工具调用 + 多轮调试 + 覆盖率收敛"全流程的 EDA Agent 公开基准，已在 4.1 节作为开放挑战提出。
8. 参考资料
- Cadence Unveils Industry's First Fully Autonomous Virtual Engineer — Cadence，2026。https://www.cadence.com/ja_JP/home/company/newsroom/press-releases/pr/2026/cadence-unveils-industrys-first-fully-autonomous-virtual.html
- Cadence Extends Chip Design Agent to Level 5 Autonomy — engineering.com，2026。https://www.engineering.com/cadence-extends-chip-design-agent-to-level-5-autonomy/
- Cadence Launches ChipStack AI Super Agent to Automate Chip Design — ENGtechnica，2026。https://engtechnica.com/cadence-launches-chipstack-ai-super-agent-to-automate-chip-design/
- Siemens Questa One Redefines IC Verification for Complex Chips — ENGtechnica，2025。https://engtechnica.com/siemens-questa-one-redefines-ic-verification-for-complex-chips
- Accellera Standards — IP-XACT — Accellera。https://www.accellera.org/downloads/standards/ip-xact
- Accellera Federated Simulation Standard PWG 介绍（含现行标准清单）— Accellera，2023。https://accellera.org/images/activities/Federated-Simulation-Standard-PWG-intro.pdf
- UCIe 3.0 Specification（2025-08-05 发布）— UCIe Consortium。https://www.uciexpress.org/post/ucie-at-the-future-of-memory-and-storage-2025
- UCIe Specifications — UCIe Consortium。https://www.uciexpress.org/specifications
- ISO 26262-11:2018 Road vehicles — Functional safety — Part 11 — ISO。https://www.iso.org/fr/contents/data/standard/06/96/69604.html
- NVIDIA GB200 NVL72 — NVIDIA 官网。https://www.nvidia.com/en-us/data-center/gb200-nvl72/
- NVIDIA GB200 NVL72 Delivers Trillion-Parameter LLM Training and Real-Time Inference — NVIDIA Developer Blog。https://developer.nvidia.com/blog/nvidia-gb200-nvl72-delivers-trillion-parameter-llm-training-and-real-time-inference/
- Synopsys Completes Acquisition of Ansys（2025-07-17）— Synopsys。https://www.synopsys.com/ja-jp/japan/press-releases/2025-07-17.html
- Advantest Pioneers a New Era of AI（ACS RTDI，2025-10-06）— Advantest。https://www.advantest.com/en/news/2025/2025100602.html
- VerilogEval v2（ACM TODAES 30(6)，2025-10-21）— ACM Digital Library。https://dl.acm.org/doi/abs/10.1145/3718088
- How AlphaChip Transformed Computer Chip Design — Google DeepMind。https://deepmind.google/blog/how-alphachip-transformed-computer-chip-design/
- SEMI 中国 · HIIC 2025 先进封装论坛官方纪要 — SEMI 中国。https://www.semi.org.cn/site/semi/article/522383c3564542f68f22bca20d0b6a43.html
- Real-World Chip Design Workflows: Technical Overview — BITSILICA。https://www.blogarama.com/technology-blogs/1445797-BITSILICA-Pvt-Ltd-Blog/70164062-real-world-chip-design-workflows-technical-overview
- IEEE 1838 Explained: How DFT Evolves for 2.5D, 3D and 3.5D ICs — LoveChip。https://www.lovechip.com/blog/ieee-1838-explained-how-dft-evolves-for-2-5d-3d-and-3-5d-ics
- AI-Assisted Chip Design 案例汇编（ER-008）— case-studies.ai。http://case-studies.ai/use-cases/engineering-and-research/ER-008-ai-assisted-chip-design/evaluation
- UCIe 与 Chiplet 互连综述 — ACM Computing Surveys。https://dl.acm.org/doi/10.1145/3819235
Hardware R&D Group
1. Introduction
1.1. The Group's Positioning
The Hardware R&D Group covers the complete chain of chips from architecture definition to volume-production delivery, divided into five directions: Chip Design (01), Chip Verification (02), Packaging (03), Testing (04), AI Infra (05).
Within the AI Harness framework, this group is the truest litmus test of whether "Harness really turns model uncertainty into engineering predictability." The reason is that the hardware domain exhibits two extreme characteristics at once:
- The most expensive feedback loop: a single tape-out at an advanced node costs in the hundreds of millions of dollars (IBS estimates $200M–$500M+ per die at 5nm–3nm, evidence level B), and design errors cannot be hot-fixed the way software can.
- The hardest ground truth: simulators, formal-verification engines, ATE testers, and measurement equipment all deliver deterministic pass/fail verdicts. The model does not need to "self-evaluate" whether it did correctly — the engineering toolchain tells it directly.
Precisely because of point 2, the L5 evaluation and observation layer of AI Harness is not something "extra to build" in the hardware domain — it is naturally existing infrastructure: coverage databases, regression farms, formal-verification proofs, and wafer measurement data are all mature verifiers. The earliest large-scale deployment of agentic AI in EDA concentrated on verification, debugging, and coverage closure rather than synthesis or place-and-route, precisely because these stages already have high-frequency, decidable, low-cost feedback loops.
图 1-1｜硬件研发组在 AI Harness 六层模型中的定位
数据来源：基于本文分析绘制的示意图。
1.2. The Group's Core Theses
Thesis 1: The Hardware R&D Group is the heaviest of all groups in L2 (Tools & Execution) and L5 (Evaluation & Observation) of the six-layer model.
- At the L2 level, EDA tools are irreplaceable. The correct posture of an agent is not to "replace the engine" but to "orchestrate the engine." Cadence ChipStack orchestrates Xcelium (dynamic simulation) and Jasper (formal verification) inside the NVIDIA OpenShell sandbox; Siemens built its own MCP (Model Context Protocol) server to expose Questa One engine capabilities to agent frameworks, explicitly emphasizing "hooking into existing simulation engines rather than replacing them." Both are ready-made L2 paradigms.
- At the L5 level, formal verification and logic equivalence checking (LEC) are the only decidable ground truth. Any AI-optimized netlist must undergo formal equivalence checking against the golden RTL to confirm functional behavior is unchanged before it can proceed to later stages.
Thesis 2: The Hardware R&D Group is the costliest of all groups in L6 (Governance & Safety).
Software defects can be patched; chip tape-out is irreversible. Therefore the Harness in this domain must be "human-in-the-loop + strong sandbox + strong audit," not fully automated. The NVIDIA OpenShell sandbox runtime is currently the most direct ready-made paradigm: it provides autonomous agents with policy control, isolation, and controlled access to tools, infrastructure, and design data to protect confidential IP. Cadence ChipStack's Level-5 full-autonomy capability runs within it.
Thesis 3: There is a significant gap between public benchmarks in EDA and real productivity, so evaluation design must guard against cheating.
On VerilogEval v2, GPT-4o's spec-to-RTL pass@1 is 63%; but according to compilations from public talks, on the more production-near CVDP benchmark the score drops to 10%–40%, and the hardest RealBench has yet to be solved by any AI system (evidence level C). This is why every AGENTS.md and SKILL.md in this group requires: do not report only academic benchmark scores — real in-project regression metrics must be reported as well.
1.3. Industry Landscape Data
| Dimension | Data | Nature of Source |
|---|---|---|
| Share of project cycle spent on RTL verification | 60%–70% (complex SoC) | Industry review, level B |
| Verification team size relative to RTL design team | 2–5x | Long-form Chinese tech-community post, level C |
| Potential design-cost savings from AI-enabled EDA | 20%–30% (Semico Research forecast); representative 14nm SoC measurement 21.3% | Compiled material, level B |
| Industry spending on AI design tools | $300M in 2023, growing 20%/yr, exceeding $500M in 2026 (Deloitte TMT Predictions) | Compiled material, level B |
| Advanced packaging market size | $69.5B in 2029, will for the first time exceed traditional packaging (SEMI China / HIIC 2025) | Official minutes, level A- |
| IC packaging & assembly market size | $61B in 2024 → $88B in 2029 (Prismark partner, HIIC 2025) | Official minutes, level A- |
| Global semiconductor market | $628B in 2024 → $908B in 2029, CAGR 7.7% | Official minutes, level A- |
| Per-die tape-out cost at advanced nodes | $200M–$500M+ at 5nm–3nm (IBS estimate) | Compiled material, level B |
It should be noted that the figures marked [To be verified] in this table come from second-hand Chinese reprints and have not been confirmed against primary sources. When citing them, the nature of the source should be stated as well, and they must not be used as the sole basis for decisions.
2. Glossary
| Term | English / Abbreviation | Definition |
|---|---|---|
| Electronic Design Automation | Electronic Design Automation，EDA | General term for the toolchain used for integrated-circuit design, simulation, verification, and physical implementation |
| Register Transfer Level | Register Transfer Level，RTL | Design abstraction level that describes circuit behavior with registers and combinational logic between registers |
| Power, Performance, Area | Power, Performance, Area，PPA | The three major metrics that measure chip implementation quality; the three usually constrain one another |
| Tape-out | Tape-out | The key milestone at which the final layout data is delivered to the foundry for manufacturing; design changes become extremely costly thereafter |
| Logic Equivalence Checking | Logic Equivalence Checking，LEC | Using formal methods to prove that the netlist before and after optimization is functionally equivalent to the golden RTL |
| Universal Verification Methodology | Universal Verification Methodology，UVM | Standardized verification-platform methodology based on SystemVerilog, IEEE 1800.2-2020 |
| Formal Verification | Formal Verification | Exhaustively proving by mathematical means that a design satisfies given properties, without relying on test vectors |
| Assertion | SystemVerilog Assertion，SVA | Describing with temporal logic the properties a design must satisfy; a common input for both formal verification and simulation |
| Coverage Closure | Coverage Closure | The process of adding stimuli and assertions so that functional and code coverage reach sign-off targets |
| Design for Test | Design for Test，DFT | Methods that insert scan chains, compression structures, and built-in self-test into the design to improve testability |
| Automated Test Equipment | Automated Test Equipment，ATE | Volume-production test machine that applies test vectors to a chip and judges pass/fail |
| Known Good Die | Known Good Die，KGD | A die that has completed wafer-level testing and been judged good; a prerequisite for Chiplet stacking |
| Universal Chiplet Interconnect Express | Universal Chiplet Interconnect Express，UCIe | Open standard for Die-to-Die interconnect, current version 3.0 (released 2025-08-05) |
| High Bandwidth Memory | High Bandwidth Memory，HBM | Memory that achieves high bandwidth through TSV vertical stacking and ultra-wide buses, JEDEC JESD235 / JESD238 / JESD270-4 series |
| Silicon Interposer | Silicon Interposer | Silicon substrate that carries high-density interconnects for multiple dies in 2.5D packaging, e.g., CoWoS-S |
| Model Context Protocol | Model Context Protocol，MCP | Open protocol that exposes external tools and data sources to agents through a standard interface |
| Model FLOPs Utilization | Model FLOPs Utilization，MFU | The ratio of actual effective compute to theoretical peak compute, a core efficiency metric for training clusters |
| Effective Training Time Ratio | Effective Training Time Ratio，ETTR | The proportion of effective training time in total occupied time, reflecting fault tolerance and recovery capability |
| Power Usage Effectiveness | Power Usage Effectiveness，PUE | The ratio of a data center's total energy use to IT-equipment energy use; closer to 1 is better |
| Defective Parts Per Million | Defective Parts Per Million，DPPM | The proportion of defective parts shipped, the bottom-line metric that test compression cannot cross |
3. Positioning Comparison of the Five Directions
3.1. High-Level Comparison Table of the Directions
| Direction | Primary Tasks | Core Executors | Deciding Ground Truth | Primary Risks | Typical Quantified Gains (Evidence Level) |
|---|---|---|---|---|---|
| 01 Chip Design | RTL generation, architecture exploration, synthesis, place & route, PPA optimization | Design Compiler / Fusion Compiler / Innovus / Yosys / Cerebrus / DSO.ai | LEC formal equivalence check + timing sign-off + synthesis pass rate | Netlist function altered; surrogate metrics (approximate wire length, congestion) diverge from final real performance | Cerebrus up to 10x productivity + 20% PPA (A); ChipStack front-end design verification up to 10x (A) |
| 02 Chip Verification | UVM platforms, SVA, coverage closure, formal verification, defect localization | Xcelium / Jasper / Questa One / VCS / Verisium | Coverage + formal proof + regression pass/fail | False closure: coverage at 100% still leaves design holes; unreachable bins waste compute | Questa One coverage acceleration 50x (A); ChipStack 40x+ speed-up of NVIDIA verification cycles (A) |
| 03 Packaging | 2.5D/3D integration, Chiplet interconnect, signal/power integrity, thermal & stress co-design | 3DIC Compiler / RedHawk-SC / Icepak / Ansys multiphysics / Xpeedic semiconductor platform | DRC/LVS + thermal-mechanical-electrical sign-off + UCIe compliance testing | Unclear multi-vendor IP boundaries; Die-to-Die protocol jungle; thermal-mechanical-electrical coupling mismatch | UCIe 3.0 reaching 48/64 GT/s (A); Synopsys–Ansys merger focusing on multi-die advanced packaging (A) |
| 04 Testing | ATE programs, DFT insertion, adaptive testing, yield analysis, failure analysis | ATE platforms (Advantest / Teradyne)、Tessent / TestMAX、diagnostic tools | DPPM, customer escape rate, yield, fault coverage | Test compression loses diagnostic capability; model generalization across process nodes is insufficient | ACS RTDI early pilot latency reduced up to 30%, test budget saved over 15% (A) |
| 05 AI Infra | Compute clusters, training & inference platforms, scheduling, interconnect, energy | Job schedulers, monitoring systems, firmware tools, MGX reference design | MFU, ETTR, share of effective training time, PUE | Frequent training interruptions; slow fault recovery; runaway energy and quota usage | GB200 NVL72 liquid cooling cuts cost and energy 25x (A); Kua'e 10k-GPU cluster Dense-model MFU 60% (B, vendor claim) |
3.2. Mapping the Five Directions to the Harness Six Layers
| Direction | L1 Context Engineering | L2 Tools & Execution | L3 Orchestration & Control | L4 Memory & State | L5 Evaluation & Observation | L6 Governance & Safety |
|---|---|---|---|---|---|---|
| 01 Chip Design | Design specs, PPA history library, process design kit | Synthesis and place & route tools (Yosys / Design Compiler / Fusion Compiler / Innovus) | Architecture-exploration DAG, parameter-space search | warm-start transfer learning (DSO.ai reusing prior design knowledge) | PPA metrics + formal equivalence check | IP isolation, OpenShell sandbox, IEEE 1735-2023 |
| 02 Chip Verification | Specs, test plans, coverage models, regression logs | Simulators + formal engines (Xcelium / Jasper / Questa One / VCS) | Regression orchestration, agent multi-step workflows | Historical regression database, coverage database | Coverage + formal verification (strongest ground truth) | Sign-off trail, human-in-the-loop, autonomy within governance boundaries |
| 03 Packaging | Multiphysics models, process design kits, Chiplet metadata | SI/PI/thermal/stress simulators (RedHawk-SC / Icepak / 3DIC Compiler) | System technology co-optimization (STCO) | Process and yield knowledge base | DRC/LVS + thermal-mechanical-electrical sign-off | Multi-vendor IP boundaries (UCIe / IP-XACT) |
| 04 Testing | Wafer maps, ATE logs, failure-sample library | ATE programs, probe stations, diagnostic tools | Adaptive test flows, real-time data infrastructure | Historical yield and defect data | DPPM + customer escape rate + yield | Automotive ISO 26262-11:2018, data does not leave the plant |
| 05 AI Infra | Cluster topology, job descriptions, fault knowledge | Schedulers, monitoring systems, firmware tools | Training fault-tolerant orchestration, elastic scheduling | Fault knowledge base, checkpoints | MFU + ETTR + PUE | Quotas, multi-tenant isolation, energy budget |
3.3. Core Bottleneck Layer for Each Direction
| Direction | Bottleneck Layer | How the Bottleneck Manifests |
|---|---|---|
| 01 Chip Design | L5 Evaluation & Observation | Long design feedback cycle — one tape-out takes months to know right from wrong; surrogate metrics diverge from real performance |
| 02 Chip Verification | L2 Tools & Execution | Heterogeneous toolchains and restricted engine licensing; agents must correctly drive commercial engines rather than build their own simulation |
| 03 Packaging | L1 Context Engineering | Heterogeneous multiphysics, multi-vendor, multi-standard data is hard to express uniformly; IP-XACT metadata is incomplete |
| 04 Testing | L6 Governance & Safety | Yield data and test programs are core assets and must not leave the enterprise; automotive scenarios add mandatory compliance constraints |
| 05 AI Infra | L3 Orchestration & Control | At the 10k-GPU scale failures become the norm; fault-tolerant orchestration and fault isolation determine effective training time |
4. Common Challenges and Countermeasures
| Challenge | Manifestation | Countermeasure |
|---|---|---|
| Expensive feedback loop; trial-and-error is unaffordable | Advanced-node tape-out costs $200M–$500M+ | Use the EDA engine as the sole judge; the model only produces candidate solutions; every candidate must pass formal equivalence checking before sign-off |
| Design data is core IP | High leakage risk for RTL, netlists, layouts, test programs, yield data | Private deployment; agents run in a sandbox runtime (NVIDIA OpenShell provides policy control and controlled access); encrypt and manage IP per IEEE 1735-2023 |
| Benchmark gap distorts self-evaluation | Academic benchmark 63% coexists with production benchmark 10%–40% | Forbid reporting only academic benchmarks; must report real metrics on the in-project regression set, and also report root-cause analysis of uncovered points |
| False closure | Coverage numbers met but the design still has holes | Distinguish code coverage from functional coverage; identify unreachable bins; assertions must be validated by formal tools, not merely pass on generation |
| Lack of a full-pipeline public EDA Agent benchmark | Existing benchmarks cover only RTL generation, not tool invocation, multi-round debugging, or coverage closure | Propose it as an open challenge (see 4.1); on the engineering side, first build an internal regression set and golden-case set |
| Insufficient model generalization across process nodes | Test and yield models fail when the node changes | Run drift monitoring before rollout; model outputs must carry confidence intervals; keep a human-review threshold |
| Fragmented protocols and standards | Multiple Die-to-Die interconnect protocols split the ecosystem | Anchor on UCIe 3.0 and IEEE 1685-2022 IP-XACT as standards, and treat other protocols as an adaptation layer |
| Risk of irreversible operations | Tape-out, sign-off, and volume-release cannot be rolled back | All irreversible actions require human confirmation + dual signature; agents have no direct trigger permission by default |
4.1. Open Challenge: The Missing Full-Pipeline EDA Agent Benchmark
The currently public hardware-related AI benchmarks (VerilogEval, CVDP, RealBench) mainly evaluate the single capability of RTL generation. Their problems are small-scale (mostly under 100 lines, single module), and agent systems can access testbenches, simulators, and waveforms for automatic debugging, so they are not comparable to single-round models.
No public EDA Agent benchmark covering the full pipeline of "tool invocation + multi-round debugging + coverage closure" has yet been found. This is a real and important gap in the industry. Its direct impact on Harness development is that this domain cannot rely on a public benchmark the way the software-engineering domain relies on SWE-bench to compare different Harness implementations horizontally — it can only rely on private regression sets inside the enterprise.
Suggested directions for the industry to pursue: build a benchmark grounded on real-project regression sets, reward coverage and the number of unique defects found, and evaluate tool-invocation trajectories; also publish failure cases to prevent the benchmark from being optimized by "cramming"-style gaming.
5. Standards and Specification Map
| Standard Number | Name | Related Directions |
|---|---|---|
| IEEE 1800-2023 | SystemVerilog — unified hardware design, specification, and verification language | 01 / 02 |
| IEEE 1800.2-2020 | UVM language reference manual | 02 |
| IEEE 1685-2022 | IP-XACT: standard structure for IP packaging, integration, and reuse | 01 / 03 |
| IEEE 1801-2024 | UPF unified power format | 01 |
| IEEE 1666-2023 | SystemC language (incl. 1666-2023/Cor 1-2025) | 01 |
| IEEE 1735-2023 | Recommended practice for encryption and management of electronic-design IP | 01 / L6 |
| IEEE 1076-2019 | VHDL language reference manual | 01 |
| IEEE 1850-2010 | PSL property specification language (status: Inactive - Reserved) | 02 |
| IEEE 1450.6.1 | Open Compression Interface (OCI) | 04 |
| IEEE 1149.1 | Test access port and boundary-scan architecture (JTAG, first released 1990) | 04 |
| IEEE 1149.6 | Boundary-scan testing of advanced digital networks | 04 |
| IEEE 1500 | Testability method for embedded cores | 04 |
| IEEE 1687 | IJTAG: access and control of instrumentation embedded within devices (published 2014) | 04 |
| IEEE 1838-2019 | Test access architecture for three-dimensional stacked integrated circuits | 03 / 04 |
| UCIe 1.0 / 1.1 / 2.0 / 3.0 | Universal Chiplet Interconnect standard (3.0 released 2025-08-05) | 03 |
| JESD235 / JESD238 / JESD270-4 / JESD79-5 | HBM、HBM3、HBM4、DDR5 | 03 / 05 |
| JESD51 series | Methods for characterizing thermal properties of packages | 03 |
| ISO 26262-11:2018 | Road vehicles — functional safety · Part 11: guidelines for semiconductor applications | 01 / 02 / 04 |
| ISO 26262-5 / -9 | Hardware-level product development / ASIL-oriented analysis (SPFM、LFM、PMHF) | 04 |
| Current Accellera standards | Portable Stimulus 2.0、SystemRDL 2.0、UCIS 1.0、OVL 2.8.1、SCE-MI 2.3、IP Tagging 1.0、Security Annotation for EDI 1.0、SystemC CCI 1.0、SystemC Synthesis 1.4.7、UVM-SystemC 1.0-beta5 | 01 / 02 |
Among these, IEEE 1685-2022, IEEE 1800-2023, IEEE 1801-2024, IEEE 1735-2023, IEEE 1666-2023, IEEE 1800.2-2020, and others are provided free to the community by Accellera through the IEEE Get program and can be prioritized in engineering implementation.
A special note for the AI Infra direction: no IEEE / ISO / JEDEC standard specific to AI compute clusters was found for this direction (except component-level standards such as HBM and UCIe). This direction relies mainly on de facto standards and vendor specifications, including the NVIDIA MGX modular server reference design, fifth-generation NVLink and NVLink-C2C, Quantum-X800 InfiniBand, Spectrum-X800 Ethernet, BlueField-3 DPU, the NVIDIA Dynamo disaggregated serving framework, and the OAM (OCP Accelerator Module) module specification. When writing related content, standard numbers must not be fabricated.
6. Document Navigation
| Document | Content | Intended Readers |
|---|---|---|
| AGENTS.md | Group-level governing specification for the Hardware R&D Group, defining the role boundaries, tool contracts, verification requirements, and safety red lines that all five directions must follow | Platform architects, EDA toolchain leads |
| SKILL.md | Group-level standard skills for the Hardware R&D Group, covering common task flows such as RTL generation, verification closure, and PPA optimization | Agent developers, EDA engineers |
| Chip Design | Chip design: RTL generation, architecture exploration, front-end design, PPA optimization | Front-end design engineers, physical design engineers |
| Chip Verification | Chip verification: UVM, formal verification, coverage closure, defect localization | Verification engineers, formal-verification engineers |
| Packaging | Packaging: advanced packaging, Chiplet, 2.5D/3D, thermal-mechanical-electrical co-design | Packaging engineers, SI/PI engineers |
| Test | Testing: ATE testing, yield analysis, DFT, failure analysis | Test engineers, yield engineers |
| AI Infra (Design) | AI Infra: compute clusters, training & inference platforms, scheduling, interconnect, energy | Cluster operations, platform engineers |
Suggested reading order: first read this page to build a global view of the five directions; then read the group-level AGENTS.md and SKILL.md to understand the common constraints; finally enter the document for your role.
7. Summary
The Hardware R&D Group is the group in the AI Harness six-layer model with the heaviest L2 and L5, and the costliest L6. As irreplaceable executors, EDA tools determine that the Harness in this domain takes the form of "orchestrating existing engines" rather than "building capability in-house"; and since formal verification and logic equivalence checking are the only decidable ground truth, the L5 evaluation layer need not be built from scratch — it should directly reuse coverage databases, regression farms, and formal proofs.
At the same time, the irreversibility of tape-out pushes L6 governance to the highest priority: human-in-the-loop, a sandbox runtime, controlled access to design data (the NVIDIA OpenShell paradigm), and IEEE 1735-2023 IP encryption management together form the non-negotiable foundation of the Harness in this domain.
What must be clearly recognized is that this domain currently has two real capability ceilings: first, the large gap between academic and production benchmarks, so the evaluation system must guard against cheating; second, the lack of a public EDA Agent benchmark covering the full pipeline, so Harness implementations cannot be compared horizontally. These two points should be key directions for future industry collaboration.
Information Gap Statement
The following items have not been confirmed by A- or B-level sources. This document has already marked them [To be verified] in the body; they are aggregated here:
- The verification team is 2–5x the size of the RTL design team (long-form Chinese tech-community post, level C).
- The current status and number of IEEE P2851 have not been officially confirmed; this group's documents will not cite it.
- The specific edition of IEC 61508 has not been confirmed on an official page; marked
[To be verified]. - ISO/SAE 21434 has not been confirmed on an official page; marked
[To be verified]. - The specific current editions of IEEE 1149.1, IEEE 1500, and IEEE 1687 have not been confirmed on the IEEE website; this group's documents state only the first-release or publication year and mark.
- UCIe 1.1's covered temperature range (some sources say 0°C–125°C) has not been officially confirmed; marked
[To be verified]. - The numbers and issuing bodies of China's Chiplet-related standards (ACC 1.0, CCLL white paper) have not been officially confirmed; marked
[To be verified]. - No publicly available standard template for AGENTS.md / SKILL.md for chip or hardware R&D was found. This group's AGENTS.md and SKILL.md are proposed drafts distilled from industry practice and vendor official documentation — not original official industry-standard text.
- No dedicated international or national standard was found for the AI Infra direction; this direction relies mainly on de facto standards, and standard numbers must not be fabricated.
- No public EDA Agent benchmark covering the full pipeline of "tool invocation + multi-round debugging + coverage closure" was found; this was raised as an open challenge in Section 4.1.
8. References
- Cadence Unveils Industry's First Fully Autonomous Virtual Engineer — Cadence，2026. https://www.cadence.com/ja_JP/home/company/newsroom/press-releases/pr/2026/cadence-unveils-industrys-first-fully-autonomous-virtual.html
- Cadence Extends Chip Design Agent to Level 5 Autonomy — engineering.com，2026. https://www.engineering.com/cadence-extends-chip-design-agent-to-level-5-autonomy/
- Cadence Launches ChipStack AI Super Agent to Automate Chip Design — ENGtechnica，2026. https://engtechnica.com/cadence-launches-chipstack-ai-super-agent-to-automate-chip-design/
- Siemens Questa One Redefines IC Verification for Complex Chips — ENGtechnica，2025. https://engtechnica.com/siemens-questa-one-redefines-ic-verification-for-complex-chips
- Accellera Standards — IP-XACT — Accellera. https://www.accellera.org/downloads/standards/ip-xact
- Accellera Federated Simulation Standard PWG Introduction (incl. current standards list) — Accellera，2023. https://accellera.org/images/activities/Federated-Simulation-Standard-PWG-intro.pdf
- UCIe 3.0 Specification (released 2025-08-05) — UCIe Consortium. https://www.uciexpress.org/post/ucie-at-the-future-of-memory-and-storage-2025
- UCIe Specifications — UCIe Consortium. https://www.uciexpress.org/specifications
- ISO 26262-11:2018 Road vehicles — Functional safety — Part 11 — ISO. https://www.iso.org/fr/contents/data/standard/06/96/69604.html
- NVIDIA GB200 NVL72 — NVIDIA official site. https://www.nvidia.com/en-us/data-center/gb200-nvl72/
- NVIDIA GB200 NVL72 Delivers Trillion-Parameter LLM Training and Real-Time Inference — NVIDIA Developer Blog. https://developer.nvidia.com/blog/nvidia-gb200-nvl72-delivers-trillion-parameter-llm-training-and-real-time-inference/
- Synopsys Completes Acquisition of Ansys (2025-07-17) — Synopsys. https://www.synopsys.com/ja-jp/japan/press-releases/2025-07-17.html
- Advantest Pioneers a New Era of AI (ACS RTDI，2025-10-06) — Advantest. https://www.advantest.com/en/news/2025/2025100602.html
- VerilogEval v2 (ACM TODAES 30(6)，2025-10-21) — ACM Digital Library. https://dl.acm.org/doi/abs/10.1145/3718088
- How AlphaChip Transformed Computer Chip Design — Google DeepMind. https://deepmind.google/blog/how-alphachip-transformed-computer-chip-design/
- Official minutes of the SEMI China · HIIC 2025 advanced-packaging forum — SEMI China. https://www.semi.org.cn/site/semi/article/522383c3564542f68f22bca20d0b6a43.html
- Real-World Chip Design Workflows: Technical Overview — BITSILICA. https://www.blogarama.com/technology-blogs/1445797-BITSILICA-Pvt-Ltd-Blog/70164062-real-world-chip-design-workflows-technical-overview
- IEEE 1838 Explained: How DFT Evolves for 2.5D, 3D and 3.5D ICs — LoveChip. https://www.lovechip.com/blog/ieee-1838-explained-how-dft-evolves-for-2-5d-3d-and-3-5d-ics
- AI-Assisted Chip Design Case Compilation (ER-008) — case-studies.ai. http://case-studies.ai/use-cases/engineering-and-research/ER-008-ai-assisted-chip-design/evaluation
- UCIe and Chiplet Interconnect Overview — ACM Computing Surveys. https://dl.acm.org/doi/10.1145/3819235