Chip Design

1. Introduction

1.1. Background

Chip design is currently under three simultaneous pressures.

First: complexity and cost. The cost of a single tape-out at an advanced node is already estimated by IBS to exceed 200 million to 500 million USD in the 5nm to 3nm range. Once a design decision goes wrong, it cannot be fixed by releasing a patch the way software can.

Second: manpower and cycle time. RTL verification of a complex SoC accounts for 60% to 70% of the project cycle. The industry continues to face tight supply of experienced front-end and physical design engineers; Cadence once estimated that the shortage of chip design and verification engineers would reach hundreds of thousands by 2030 (this figure is a secondary citation).

Third: the explosion of the design space. The full flow from RTL to GDSII involves hundreds of adjustable tool parameters — synthesis effort levels, physical optimization knobs, timing constraints, mapping strategies, floorplan hints, and so on. Manual trial-and-error search quickly fails in the face of such high dimensionality.

The emergence of large models offers a direct path to relieve the third pressure: hand over the exploration of parameter space to reinforcement learning or agents, and let natural language and specifications express design intent. But the first two pressures determine that AI applications in chip design cannot adopt the "generate-and-deliver" paradigm; they must be constrained by a strict engineering Harness.

1.2. Definition and Scope

Chip design covers the whole process from architecture definition to layout delivery (RTL-to-GDSII). In the AI Harness context, it specifically refers to the following stages in which agents participate or take the lead:

Boundary note: Under an Agentic architecture, design and verification are increasingly inseparable (ChipStack covers both front-end design and verification). The division of labor between this direction and Chip Verification is: this direction focuses on "how to build the design and achieve better PPA", while the verification direction focuses on "how to prove it is correct".

1.3. Positioning in the AI Harness System

图 1-1｜芯片设计 · 在 AI Harness 六层模型中的定位

数据来源：基于本文分析绘制的示意图。

The mapping of chip design onto the six-layer model is as follows:

Core judgment: the bottleneck of the chip design direction lies in the L5 evaluation and observation layer. Unlike the verification direction, the design side lacks high-frequency, low-cost, and decidable feedback signals — a single run of synthesis and place-and-route takes hours to days, while the final performance correctness can only be confirmed once the chip returns from tape-out. This directly leads to two engineering consequences:

1. The design side relies heavily on surrogate metrics (approximate wirelength, approximate congestion, estimated timing), and there is a disconnect between surrogate metrics and the chip's final real performance (see the counter-evidence in 3.1.3).
2. Logic equivalence checking (LEC) becomes the only reliable hard gate on the design side: any AI-optimized netlist must undergo logic equivalence checking against the golden RTL to confirm that functional behavior is unchanged before it can proceed to the next stage.

1.4. Current State of Development

The benchmark gap is a reality this direction must face. VerilogEval v2 (NVIDIA, ACM TODAES 30(6), 2025-10-21) gives spec-to-RTL pass@1 of: GPT-4o 63%, Llama3.1-405B 58%, RTL-Coder 6.7B 34% (level A). Multi-agent systems can reach MAGE 95.7%, VerilogCoder 94.2% (level B), but the paper authors themselves point out that VerilogEval problems are all under 100 lines and single-module, and agents can access testbenches, simulation and waveform-based automatic debugging, so they are not comparable to single-pass models.

Based on public presentations (level C): results above 70% on VerilogEval drop to 10% to 40% on the more production-like CVDP benchmark, while no AI system has yet solved a single problem on the most difficult RealBench. NVIDIA's domain model ChipNeMo scores 43.4% on RTL generation, below general GPT-4's 60%; its real value lies in Q&A, script generation and bug summarization (level C).

2. Glossary

3. Case Studies

3.1. Google AlphaChip: Reinforcement-Learning-Driven Placement Planning

Evidence level: A (Google DeepMind official / Nature paper); counter-evidence level C

3.1.1. Background

Chip floorplanning is one of the most time-consuming and most automation-resistant stages of chip design, which has not been effectively automated for more than sixty years. The difficulty lies in the fact that the effect of a placement decision can only be evaluated after routing completes and timing converges, making the feedback chain extremely long; and every generation of TPU needs high-quality macro placement.

3.1.2. Approach

Google models placement as a "game": starting from an empty grid, components are placed one by one and rewarded according to the final placement quality. The core technology is the edge-based graph neural network (Edge-GNN), used to learn relationships among interconnected components and generalize across chips. The training strategy is to pre-train on past TPU blocks first, then fine-tune on the current TPU block.

The key engineering characteristic of this approach is that it explicitly constructs a closed loop between the L4 memory layer (transfer of pre-trained knowledge across chip generations) and the L5 evaluation layer (using final placement quality as the reward function) — this is precisely the typical form of the AI Harness in the hardware design domain.

3.1.3. Results

• Applied to TPU v5e, v5p and Trillium (6th generation), as well as Google Axion (the first Arm-based data center CPU).
• On Trillium, AlphaChip placed 25 blocks, reducing wirelength by 6.2% versus the physical design team.
• Completed macro placement comparable to or better than human experts in about 6 hours, versus weeks to months for manual work (Nature 594:207-212, 2021).
• In 2024-09 it released pre-trained checkpoints and was formally named AlphaChip; MediaTek has extended the method to its most advanced chips (including the Samsung phone Dimensity flagship 5G).

Counter-evidence that must also be recorded (separating facts from opinion):

In 2025, the UCSD Andrew Kahng team used Google's publicly released pre-trained models and, after ample compute for training to convergence, found that classical simulated annealing could still match or beat them on public benchmarks, and faster; ChiPBench points out that reinforcement learning optimizes surrogate metrics (approximate wirelength, approximate congestion) that are disconnected from the chip's final real performance. This set of evidence comes from secondary Chinese reposts and is marked [To be verified], but its viewpoint is significant: "already in production" and "scientifically superior" are two different things, and therefore in the chip design direction, improvements in surrogate metrics must not be directly equated with product value.

3.2. Synopsys DSO.ai and Cadence Cerebrus: Large-Scale Deployment of PPA Optimization

Evidence level: A- / B

3.2.1. Background

The full RTL-to-GDSII flow has hundreds of tool parameters that need tuning, including synthesis effort levels, physical optimization knobs, timing constraints, mapping strategies, floorplan hints, and so on. Manual trial-and-error is not only slow but also highly dependent on the experience of a few senior engineers, making it hard to replicate and pass on.

3.2.2. Approach

Reinforcement learning automatically adjusts the combinations of the above tool parameters, using the PPA results of real EDA tools as reward signals after each iteration, gradually converging to better solutions. Engineering-wise, two points are emphasized: first, warm-start — initializing new tasks with knowledge from previous designs, so the more it is used, the faster it becomes; second, concurrent exploration — pruning the huge search space into small-scale experiments that can run in parallel.

3.2.3. Results

Synopsys DSO.ai

• A 5nm high-performance CPU core: initial frequency stuck at 1.75 GHz, target 1.95 GHz. The theoretical search space was 100 million options; AI pruned it to 30 concurrent runs × 3 iterations (about 90 trials), reaching 1.95 GHz (+12%) in 2 days with zero human intervention, while power dropped to 27.9 mW and area met target. The traditional approach required about 1 month of manual tuning by senior engineers.
• The 5nm chip design optimization cycle was shortened from 6 months to 6 weeks (−75%).
• Samsung 3nm mobile processor: frequency +300 MHz, dynamic power −10%.
• SK hynix flash memory: cell area −15%, 5% die shrink.

Cadence Cerebrus

• Official claim: up to 10× productivity + 20% PPA improvement; cumulatively over 1,000 tape-outs.
• On Cadence's Q4 2025 earnings call, CEO Anirudh Devgan stated that PPA improvement in back-end physical design is on the order of 7%, 10% and 12%, equivalent to gaining half to a full process-node migration.
• Customer results: Samsung achieved 4× productivity on SF2 tape-out; Altera achieved 7 to 10× productivity improvement in the RTL writing stage.
• Imagination Technologies used Cerebrus in the cloud to optimize low-power IP blocks, reaching design goals with far fewer iterations than baseline.

Engineering key point: all the PPA optimization results above must pass logic equivalence checking to confirm that functional behavior is unchanged before delivery. This is an unskippable hard gate for this direction.

3.3. Cadence ChipStack: An Agent Super-Agent for Design and Verification

Evidence level: A (Cadence official press release)

3.3.1. Background

The semiconductor industry faces a severe shortage of senior engineering talent; front-end design and verification (RTL writing, testbenches, test plans, regression, debugging) has long relied on manual work, with a great deal of hand-off between stages.

3.3.2. Approach

Cadence acquired ChipStack (founded in Seattle in 2023), which came out of the AI2 (Allen Institute for AI) incubator, in 2025-11, and released ChipStack AI Super Agent on 2026-02-10. Its architectural characteristics are highly instructive for Harness design:

• Orchestrate rather than replace: ChipStack orchestrates multiple "virtual engineers", all calling Cadence's underlying EDA tools, and still relies on sign-off-precision results from Xcelium (dynamic simulation) and Jasper (formal verification) underneath.
• Pluggable models: supports cloud and local frontier models, including the customizable open-source NVIDIA Nemotron + NeMo, as well as cloud-hosted models such as OpenAI GPT; natively compatible with Codex and Claude Code.
• Explicit design intent: combines Mental Models with automated formal test-plan generation.
• Built-in governance (L6 paradigm): runs inside the NVIDIA OpenShell sandbox runtime, providing policy control, isolation, and controlled access to tools, infrastructure and design data for autonomous agents, in order to protect confidential IP.

On 2026-06-01 it announced expansion to Level-5 full autonomy at Computex, with Level-5 capabilities opening to early customers in the second half of 2026.

3.3.3. Results

• Official claim: up to 10× productivity improvement in front-end design and verification.
• Early deployment customers: NVIDIA, Altera, Qualcomm, Tenstorrent.
• Arvind Vidyarthi, Altera's senior director of engineering: roughly 10× reduction in verification effort in some areas, with deeper functional coverage on the most complex designs.
• Daniel Cummings, principal engineer of Tenstorrent's RISC-V cores: across 3 key design modules and a 3-month evaluation, formal verification time reduced by up to 4×.
• Inside NVIDIA: each engineer ran hundreds of Xcelium dynamic simulations + Jasper formal verifications with ChipStack, accelerating the RTL verification cycle by more than 40×, with a typical 5-week verification loop shortened to under 1 day.

What this case teaches for Harness: ChipStack is a ready-made paradigm combining "L2 orchestration of existing engines + L5 engine results as ground truth + L6 sandbox governance" in one, and can be directly mapped to this direction's AGENTS.md and SKILL.md.

4. Practice Standards

Nature statement: the following AGENTS.md and SKILL.md are recommended drafts distilled from public industry practice, not official industry standard text. As of the time this document was written, no public AGENTS.md or SKILL.md standard template targeting the chip design direction was found.

4.1. AGENTS.md Specification

4.1.1. AGENTS.md (Chip Design Direction)

# AGENTS.md —— 芯片设计

> 本文为基于行业实践提炼的建议稿，非官方行业标准原文。

## 角色与边界
- 角色：芯片设计智能体，负责架构探索、RTL 生成、前端设计、PPA 优化与布局规划辅助。
- 编排引擎，不替代引擎：所有 PPA、时序、面积结论必须由 Design Compiler / Fusion Compiler /
  Innovus / PrimeTime / Yosys 等真实工具给出，模型不得推断或估算后充当结论。
- 不负责：流片放行签字、代工厂工艺选择、ASIL 等级判定、商务决策。

## 环境假设
执行前必须显式声明：
- 工艺节点与代工平台；PDK 版本；标准单元库与工艺角（PVT corner）。
- 综合工具及版本（Yosys / Design Compiler / Fusion Compiler）。
- 物理实现与签核工具及版本（Innovus / ICC2 / PrimeTime / Calibre）。
- 形式验证工具及版本（Jasper / VC Formal / Questa Formal / Conformal）。
- 语言与格式基线：SystemVerilog（IEEE 1800-2023）、UPF（IEEE 1801-2024）、
  SystemC（IEEE 1666-2023）、VHDL（IEEE 1076-2019）、IP-XACT（IEEE 1685-2022）。
- 车规场景须额外声明目标 ASIL 等级与 ISO 26262-11:2018 适用条款。
- 未声明环境时，禁止产出与 PPA、时序、面积相关的任何结论。

## 上下文加载顺序（Context Budget）
1. 设计规范相关章节、接口定义、时序与功耗约束（SDC / UPF）。
2. 相关 IP 的 IP-XACT 元数据与集成约束。
3. 基线 PPA 报告与历史优化记录。
4. 项目编码规范、命名约定、既往设计决策记录（ADR）。
5. 若具备条件，加载以知识图谱表达的设计意图（Mental Models）作为生成与验证的共同真实来源。
- 原始网表、完整版图、大规模日志不进上下文，以路径引用 + 工具查询代替。

## 工具契约
- 优先为各 EDA 引擎封装 MCP（Model Context Protocol）服务器，通过标准化接口调用。
- 工具返回值必须包含：退出码、日志路径、关键指标数值、随机种子、工具版本。
- 同一任务在相同种子下必须可复现；所有调用须记录完整命令行或脚本。
- 并发探索须声明并发上限与 EDA 授权配额，不得超过声明值。
- 不可逆工具（流片数据导出、签核放行）默认不授予直接调用权限，只产出待审批产物。

## 任务执行流程（SOP）
- S1 需求解析：分解为可判定子目标，每个子目标有明确工具可判定。
- S2 基线建立：跑基线综合与实现，记录 PPA、种子、脚本版本。
- S3 候选生成：产出候选 RTL 或参数组合，每个候选附理由与预期影响。
- S4 工具判定：调用综合、布局布线、时序分析得到客观数值。
- S5 差异分析：与基线逐项对比，改善项与恶化项同时报告，恶化项给出根因。
- S6 等价性检查：若改动网表或 RTL，执行 LEC 并与黄金 RTL 比对。
- S7 证据打包：命令、脚本、日志路径、数值、种子、版本齐备。
- S8 人工确认：涉及签核与流片的结论进入人工审批队列。

## 验证与证据要求
- 形式等价性检查（LEC）为硬门槛：任何 AI 优化后的网表必须与黄金 RTL 做 LEC，
  确认功能行为未改变，报告可追溯。
- 时序必须签核：涉及时序的结论以 PrimeTime 等签核精度工具结果为准，禁止用估算值替代。
- 代理指标（近似线长、近似拥塞）仅作过程信号，不得作为最终结论依据。
- 综合通过率为必需指标：生成的 RTL 必须通过 lint 与综合，禁止"看起来对"即交付。
- 每条结论须附：工具名 + 版本 + 命令或脚本 + 日志路径 + 关键数值 + 种子。

## 失败与升级策略
- 连续 3 轮迭代 PPA 无改善 → 升级人工，输出未改善点根因分析。
- 模型提出非常规结构（异常 latch 结构、非典型逻辑风格、反直觉参数组合）
  → 必须人工复核后才可进入签核。
- LEC 不通过 → 立即回退至上一基线，禁止在不等价的基础上继续优化。
- 综合或签核工具报未知错误 → 停止执行，不得绕过授权或改参数强行绕过。
- 升级时须交付：已完成的证据包 + 失败点定位 + 下一步可执行的具体命令。

## 安全与合规红线
- 自主智能体必须在沙箱运行时内执行（参考 NVIDIA OpenShell：策略控制、隔离、
  对工具/基础设施/设计数据的受控访问）。Cadence ChipStack Level-5 即运行于其中。
- RTL、网表、版图属企业核心 IP，不得离开企业网络边界，不得作为外部模型训练输入。
- 第三方 IP 按 IEEE 1735-2023 做加密与权限管理，不得解密、反推或转储其内部实现。
- 车规场景须符合 ISO 26262-11:2018：SEooC 假设清单（AoU）、FMEDA、DFA、
  SPFM / LFM / PMHF 三项硬件架构度量、软错误（SEU / SET / MBU）分析。
- 所有工具调用与人工确认写入不可篡改审计日志。
- 云上并发与高性能计算须设置预算护栏，超限即熔断。

## 禁止事项
- 禁止编造或臆测网表、时序报告、PPA 数值、综合结果。
- 禁止输出"应该没问题""大概率通过"等不可判定表述。
- 禁止用学术基准（VerilogEval 63% 等）成绩替代项目内真实回归指标。
- 禁止绕过 LEC 直接采纳 AI 优化网表。
- 禁止把设计数据上传至未授权外部服务。
- 禁止虚构标准编号；未确认标准一律标注 [待核实]；不引用未获官方确认的编号。
- 禁止在无人确认下触发流片、签核放行等不可逆动作。
- 禁止为达成 PPA 目标而放宽时序约束或删除设计规则检查项。

## 输出格式
- 首行给出可判定结论（通过 / 不通过 / 部分通过 + 阻塞项）。
- 证据表：工具、版本、命令或脚本、日志路径、关键数值、种子、与基线差值。
- 差异说明：改善项与恶化项逐条列出，恶化项附根因。
- 风险与假设：列出结论依赖的 PVT 角、库版本、约束前提。
- 待人工确认项：需人类决策的事项与建议动作。
- 数值规范：参数带单位；范围用 ~ 连接；百分比数值与 % 之间不留空格。

## 评估与自检
- 本轮所有结论是否都有真实工具输出支撑？有无任何一条来自模型推断？
- 若改动网表或 RTL，是否已完成 LEC 并留存报告？
- 是否同时报告改善项与恶化项？是否只报了有利指标？
- 代理指标改善是否已在签核后真实 PPA 上得到验证？
- 结论依赖的工艺节点、PDK 版本、工具版本是否已在环境假设中声明？
- 是否发生设计数据越界访问？审计日志是否完整？
- 输出中是否残留 XX、___ 等非标准占位符？
- Harness 或提示词变更后，是否在固定黄金案例集上回归并报告与上一版本的差值？

4.2. SKILL.md Specification

4.2.1. SKILL.md (Chip Design · RTL Generation and PPA Optimization)

---
name: chip-design-rtl-and-ppa
description: 芯片设计方向的 RTL 生成与 PPA 优化技能。当需要依据规范生成可综合 RTL、
  修复 lint 问题、探索综合与物理实现参数空间以改善 PPA，并要求形式等价性检查通过时使用。
version: 1.0
created: 2026-09-12
---

# 芯片设计 · RTL 生成与 PPA 优化

> 本文为基于行业实践提炼的建议稿，非官方行业标准原文。

## 适用场景
- 依据设计规范生成可综合 RTL（spec-to-RTL），或从自然语言需求生成实现（NL-to-GDSII 中的前端环节）。
- lint 与综合错误的自动定位与修复。
- 综合与物理实现参数空间探索，改善功耗、性能、面积。
- 多方案比选的设计空间探索（在线时序与面积预估）。
- 车规场景下的安全机制实现辅助（双核锁步、ECC、BIST 等）。

## 前置条件
- 已声明工艺节点、PDK 版本、标准单元库与 PVT 角。
- 已声明综合、物理实现、签核、形式验证工具及版本。
- 存在可重跑的基线综合与实现流程（含固定种子与脚本版本）。
- 智能体运行于隔离运行时，工具与数据访问受策略控制。
- EDA 授权数量与并发上限明确。
- 具备判定器：至少能给出综合通过/失败、时序收敛/违例、LEC 等价/不等价的确定性结论。

## 输入
| 输入项 | 说明 | 必需 |
|---|---|---|
| 设计规范 | 目标章节、接口定义、时序与功耗约束 | 是 |
| 现有源文件 | RTL、SDC、UPF、IP-XACT 元数据 | 是 |
| 环境清单 | 工艺节点、PDK 版本、工具及版本 | 是 |
| 基线 PPA 报告 | 基线时序、功耗、面积、拥塞 | 是 |
| 目标指标 | PPA 目标值与不可突破的边界 | 是 |
| 资源配额 | 并发数、CPU 上限、预算上限 | 否 |

## 输出
| 输出项 | 说明 | 必需 |
|---|---|---|
| 可判定结论 | 通过 / 不通过 / 部分通过 + 阻塞项 | 是 |
| 证据表 | 工具、版本、命令或脚本、日志路径、关键数值、种子、与基线差值 | 是 |
| 变更清单 | 改动的 RTL、约束、工具参数及理由 | 是 |
| 差异分析 | 改善项与恶化项，恶化项附根因 | 是 |
| LEC 报告 | 形式等价性检查报告（改动网表或 RTL 时必需） | 条件必需 |
| 代理指标声明 | 明确标注哪些数值为签核前代理指标 | 是 |
| 待人工确认项 | 非常规结构复核、签核放行、流片放行 | 是 |

## 执行步骤
1. 环境校验：核对 PDK、库版本、工具版本、判定器可用性；缺失即停止。
2. 基线重跑：固定种子重跑基线综合与实现，记录 PPA 与脚本版本。
3. 候选生成：产出候选 RTL 或参数组合，每个附理由与预期影响；优先复用既有模块与 IP。
4. 工具判定：调用综合、布局布线、时序分析；记录完整命令行、退出码、日志路径、种子。
5. 差异分析：与基线逐项对比；恶化项必须有根因解释。
6. 等价性检查：改动网表或 RTL 时执行 LEC，与黄金 RTL 比对。
7. 签核校验：涉及时序与功耗的结论以签核精度工具为准。
8. 证据打包与交付：标注代理指标，列出待人工确认项，写入审计日志。

## 质量标准（DoD）
- 综合通过率 100%（lint 无 error，综合无 error）。
- 形式等价性检查 100% 通过，报告可追溯。
- 时序结论来自签核精度工具，非估算。
- 改善项与恶化项同时报告，恶化项给出根因。
- 代理指标（近似线长、近似拥塞）明确标注，不与签核后真实 PPA 混用。
- 每条结论附工具名 + 版本 + 命令或脚本 + 日志路径 + 关键数值 + 种子。
- 无设计数据越界访问；审计日志完整。
- 输出中无 XX、___ 等非标准占位符；未确定项统一标注 [待填写] 或 [待核实]。
- 参考阈值：行业内公开的官方口径为 Cadence Cerebrus 最高 10 倍生产力 + 20% PPA 改善、
  累计超 1,000 次流片（级别 A）；Samsung 在 SF2 tape-out 上 4 倍生产力、
  Altera 在 RTL 编写环节 7~10 倍生产力（级别 A-）。这些为厂商口径，
  项目内应建立自己的基线与目标，不得直接套用。

## 常见失败与处理
| 失败模式 | 现象 | 处理 |
|---|---|---|
| 代码幻觉 | 伪造端口、错标信号、引用不存在模块 | 立即 lint + 综合校验；失败项回退重生成，不进入后续流程 |
| 提示模糊 | 生成结果偏离规范 | 补全规范章节与接口定义后重跑，不做猜测式实现 |
| 工具特异性差异 | 同一 RTL 在不同综合器结果不同 | 固定工具与版本，证据表显式标注 |
| 无限循环 | 反复重生成无收敛 | 带短期记忆的重试上限 3 轮，超限升级人工 |
| 代理指标脱节 | 线长或拥塞改善但签核 PPA 未改善 | 以签核后真实 PPA 为准，回退代理指标优化结果 |
| LEC 不等价 | 优化后网表与黄金 RTL 功能不一致 | 立即回退，禁止在不等价基础上继续优化 |
| 非常规结构 | 出现异常 latch 或非典型逻辑风格 | 强制人工复核后才可进入签核 |
| 授权不足 | 并发探索被授权限制中断 | 降低并发并记录，不得绕过授权机制 |

## 示例
任务：某 5nm 高性能 CPU 核主频从 1.75 GHz 提升至 1.95 GHz，功耗不劣化。
1. 环境校验：确认 5nm PDK 版本、Fusion Compiler 版本、PVT 角、并发配额。
2. 基线重跑：固定种子重跑基线，记录基线主频 1.75 GHz、功耗、面积。
3. 候选生成：把工具参数空间剪枝为 30 个并发运行 × 3 轮迭代的试验方案。
4. 工具判定：并发执行，记录每轮主频、功耗、面积与脚本版本。
5. 差异分析：达成 1.95 GHz（+12%），功耗降至 27.9 mW，面积达标。
6. 等价性检查：与黄金 RTL 做 LEC，功能行为未改变。
7. 签核校验：以签核精度工具确认时序收敛。
8. 交付：结论"通过"；证据表含工具版本、命令、日志路径、种子、与基线差值；
   待人工确认项为签核放行。
（本示例的结构参考已公开的 DSO.ai 5nm CPU 案例，级别 B。）

## 关联
- 与验证方向的耦合：Cadence ChipStack 同时覆盖设计与验证，
  在 NVIDIA 场景的 40 倍提速正是 Xcelium 动态仿真 + Jasper 形式验证组合跑出来的，
  说明设计与验证在 Agentic 架构下已不分离。
- 与封装方向的耦合：Synopsys 完成收购 Ansys（2025-07-17）后计划推出多物理场集成能力，
  重点是多裸片先进封装，设计阶段的 PPA 目标将延伸到封装级。

4.3. Implementation Checklist

5. Summary

The chip design direction is the link in the hardware domain where the AI Harness has the most expensive feedback but also the most direct returns. Its engineering form can be summarized in three statements:

1. Orchestrate engines, do not replace them. The EDA toolchain is an irreplaceable executor; the value of agents lies in automating the exploration of hundreds of parameter knobs, not in playing the role of a synthesizer or placer themselves.
2. Logic equivalence checking is the only hard gate. Any AI-optimized netlist must undergo LEC against the golden RTL to confirm that functional behavior is unchanged. This red line is not relaxed for efficiency gains.
3. Surrogate metrics are not product value. AlphaChip's public case and the counter-evidence from the Kahng team and ChiPBench jointly show that being in production and being scientifically superior are two different things. Improvements in surrogate metrics must be verified on real post-sign-off PPA.

At the same time, the benchmark gap must be clearly recognized: GPT-4o's 63% pass@1 on VerilogEval v2 versus the 10% to 40% on the production-like CVDP benchmark () and RealBench's 0 solutions to date () differ by an order of magnitude. This gap requires the Harness in the chip design direction to prevent cheating in evaluation — it must not report only academic benchmarks but must report metrics on a real in-project regression set.

Finally, what ChipStack demonstrates — "full autonomy inside a sandbox + the engine providing ground truth + human supervision at key decision points" — is currently the public paradigm closest to the ideal Harness form for this direction.

Information Gap Statement

The following items have not been confirmed by A-level or B-level sources and are marked [To be verified] in the body text:

1. CVDP 10% to 40% and RealBench's 0 solutions to date from NVIDIA Mark Ren's 2025 talk (level C).
2. The comparison of ChipNeMo RTL generation 43.4% versus GPT-4 60% (level C).
3. 3nm design cost exceeding 600 million USD, 2nm projected to exceed 1 billion USD, and a single 2nm mask costing 350,000 USD (level C).
4. About 30% yield for an 800 mm² large die versus 70% to 80% yield for 4×200 mm² chiplets (level C).
5. Cadence's estimate of a shortage of hundreds of thousands of chip design and verification engineers by 2030 (level C).
6. SemiAnalysis performance figures for OpenAI Jalapeño: SIMD unit area reduced 8%, matrix engine area reduced 10%, and Codex writing cores 1.5 to 1.8× faster than the best human engineers (level C). Among these, "tape-out completed in about 9 months" is supported by TrendForce citing Reuters, level B.
7. Domestic EDA agent items: UniVista UDA 2.0 (2026-03), Rapidus Raads generator (2025-12), and BanXin/DVcrew (2025-11) (level C; sources may include AI-generated content).
8. Specific metrics of open-source RTL models (RTLCoder-7B, CodeV-R1, MeltRTL, InCoder-32B, RTL-CLAW, FormalRTL) (level C; some items may be fabricated or misdated, and are recommended for item-by-item verification before use).
9. IEEE P2851 is not officially confirmed and this document does not cite it. The specific edition of IEC 61508 and ISO/SAE 21434 are not confirmed on official pages and are marked [To be verified].
10. Huawei, Cambricon and VeriSilicon have no official public data on AI-assisted chip design, so this document does not force-fit any.

6. References

1. How AlphaChip Transformed Computer Chip Design — Google DeepMind. https://deepmind.google/blog/how-alphachip-transformed-computer-chip-design/
2. A graph placement methodology for fast chip design — Nature 594:207-212 (2021). https://www.nature.com/articles/s41586-021-03544-w
3. Cadence Unveils Industry's First Fully Autonomous Virtual Engineer — Cadence, 2026. https://www.cadence.com/ja_JP/home/company/newsroom/press-releases/pr/2026/cadence-unveils-industrys-first-fully-autonomous-virtual.html
4. Cadence Extends Chip Design Agent to Level 5 Autonomy — engineering.com, 2026. https://www.engineering.com/cadence-extends-chip-design-agent-to-level-5-autonomy/
5. Cadence Launches ChipStack AI Super Agent to Automate Chip Design — ENGtechnica, 2026. https://engtechnica.com/cadence-launches-chipstack-ai-super-agent-to-automate-chip-design/
6. VerilogEval v2 — ACM Transactions on Design Automation of Electronic Systems 30(6), 2025-10-21. https://dl.acm.org/doi/abs/10.1145/3718088
7. Real-World Chip Design Workflows: Technical Overview — BITSILICA. https://www.blogarama.com/technology-blogs/1445797-BITSILICA-Pvt-Ltd-Blog/70164062-real-world-chip-design-workflows-technical-overview
8. AI-Assisted Chip Design Case Compilation (ER-008) — case-studies.ai. http://case-studies.ai/use-cases/engineering-and-research/ER-008-ai-assisted-chip-design/evaluation
9. UniVista UDA Official Release — UniVista. https://www.univista-isg.com/site/news_detail/468
10. Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach — MosChip. https://moschip.com/blog/semiconductor-design-solutions/accelerating-rtl-design-with-agentic-ai-a-multi-agent-llm-driven-approach
11. Accellera Standards — IP-XACT — Accellera. https://www.accellera.org/downloads/standards/ip-xact
12. ISO 26262-11:2018 Road vehicles — Functional safety — Part 11 — ISO. https://www.iso.org/fr/contents/data/standard/06/96/69604.html
13. AlphaChip-related controversy and ChiPBench discussion (Chinese repost) — EE Focus. https://www.eefocus.com/article/2068892.html
14. AI Chip Design Analysis (bilingual) — Computing Life. https://grapeot.me/share/ai-chip-design-en-20260624.html
15. Reports on OpenAI's in-house chips — TrendForce. https://www.trendforce.com/news/2026/09/09/news-openai-says-it-is-working-with-samsung-on-next-gen-chips-ties-could-expand-beyond-memory/
16. Synopsys Completes Acquisition of Ansys (2025-07-17) — Synopsys. https://www.synopsys.com/ja-jp/japan/press-releases/2025-07-17.html