Packaging

1. Introduction

1.1. Background

Packaging is rising from being a "back-end process for protection and interconnection" into the "main battleground that determines system performance." This shift is driven by three forces:

First: declining economics of advanced nodes. The area limit of a monolithic SoC is constrained by reticle size; the yield penalty of continuing to increase area rises sharply, making Chiplet the mainstream architecture of the post-Moore era.

Second: AI's exponential demand for bandwidth. AI accelerators are limited by memory bandwidth rather than arithmetic throughput. HBM provides bandwidth through TSV vertical stacking and ultra-wide buses, and this must rely on 2.5D/3D advanced packaging.

Third: a structural reversal in market size. According to the SEMI China HIIC 2025 minutes, the advanced packaging market is projected to reach USD 69.5 billion by 2029, surpassing traditional packaging for the first time; the IC packaging and assembly market grows from USD 61 billion in 2024 to USD 88 billion in 2029.

The core difficulty of advanced packaging is that it is a strongly coupled multiphysics problem: thermal, stress, power integrity, and signal integrity interact within a single package, and a mismatch in any one dimension leads to overall failure. This shapes what the packaging direction demands from AI Harness — not "generating a piece of code," but "co-optimization and sign-off on heterogeneous data."

1.2. Definition and Scope

The packaging direction covers the full design, simulation, and verification process from bare die to finished package; in the AI Harness context it refers specifically to what agents participate in or drive:

Boundary note: packaging is strongly coupled with the testing direction (see [03 related]) — a Chiplet must first pass KGD (Known Good Die) testing before stacking; its coupling with the design direction lies in the fact that, after Synopsys completes its acquisition of Ansys, PPA targets will extend from the die level to the package level.

1.3. Position in the AI Harness System

图 1-1｜封装方向在 AI Harness 六层体系中的定位

数据来源：基于本文分析绘制的示意图。

Core judgment: the bottleneck of the packaging direction lies at the L1 Context Engineering layer. The reason is that the data involved in packaging design is extremely heterogeneous: geometry (layout and bump map), electrical (SI/PI), thermal (temperature field), mechanical (stress and warpage), and standards (UCIe, IP-XACT, JEDEC). These data belong to different tools, different coordinate systems, and different precision requirements; organizing them into model-understandable context is more challenging than the capability of the model itself.

A noteworthy standards evolution: UDA (UCIe DFx Architecture) introduced in UCIe 2.0 builds testing, telemetry, and debugging capabilities into each chiplet, covering the full SiP lifecycle from sort to field management. This means the packaging standard itself has already embedded observability — this is the special form of Harness's L5 evaluation layer in the packaging domain, and it also shows that standards setters are already preparing for "agent-observable packaging systems."

1.4. Current Status

UCIe standard evolution (Level A)

UCIe consortium board members include ASE, Alibaba, AMD, Arm, Google Cloud, Intel, Meta, Microsoft, NVIDIA, Qualcomm, Samsung, TSMC. Specifications must be requested via the UCIe website.

HBM standards and specifications

Key physical parameters (Level B)

Other related standards: IEEE 1685-2022 (IP-XACT, the data-exchange foundation for Chiplet integration), IEEE 1838-2019 (3D stacking test access architecture), IEEE 1149.1 / 1149.6 / 1500 / 1687 (the standards family that Chiplet DfT relies on).

Industry consensus (SEMI China HIIC 2025 official minutes, Level A-)

• Yao Li of Unisoc: innovative solutions, technologies, and materials (high-thermal-conductivity molding compounds, high-thermal-conductivity substrates, etc.) can improve performance, and design is the decisive factor in quality, in which efficient simulation is key; he also highlighted the trend of EMI moving from large systems into the package body.
• Jian Chen of Alibaba Cloud: UCIe will continue to increase bandwidth density and cover a more comprehensive set of packaging scenarios; 3D packaging will become an effective way to address the transistor-density bottleneck.
• Zhengda Wu of Payton Technology: 3.5D packaging, combining 3D stacking with 2.5D interconnection, is a way to balance cost and performance; future directions include interposers, glass carriers, board-level packaging, automation, and silicon photonics.
• Lam Research: shifting from wafer-level to panel-level packaging (PLP) is an important trend; besides larger size, yield is also a key objective.
• E. Jan Vardaman of TechSearch International: silicon interposer technology has matured but is limited in size by the increasing number of HBM stacks; RDL technology is already in production, with reliability data published and practically validated; glass substrate technology remains at the R&D stage.
• Fengwen Mu of Qinghe Jingyuan: hybrid bonding will become key to future 3D integration of chiplets and wafers.

2. Glossary

3. Case Studies

3.1. TSMC CoWoS and HBM Stacking: Scaling 2.5D Integration

Evidence level: B (ai-mst.com deep analysis / IntuitionLabs citing JEDEC and vendor official sources); GB200 data is Level A (NVIDIA official website)

3.1.1. Background

AI's exponential demand for compute and bandwidth, combined with the declining economics of Moore's law at advanced nodes, has made Chiplet the mainstream architecture. As the most mainstream 2.5D integration platform, CoWoS has long been oversubscribed, with lead times exceeding 50 weeks.

3.1.2. Approach

A silicon interposer is introduced between the die and the organic substrate, leveraging silicon's ultra-high routing density to achieve high-speed multi-die interconnect. Three variants:

• CoWoS-S: full silicon interposer.
• CoWoS-L: localized silicon bridge + organic substrate.
• CoWoS-R: replaces the silicon interposer with RDL.

On the HBM side, 2.5D integration uses TSV vertical vias + micro-bumps + a silicon interposer. The key engineering insight is that a single HBM3 stack exposes a 1024-bit bus (versus 64-bit for a single DDR5 channel), and bus width, rather than clock frequency, is the main source of the bandwidth gain; silicon interposer trace lengths under 1 mm relax signal-integrity constraints and allow lower voltages.

3.1.3. Results

• Silicon interposer routing pitch is as fine as 0.4 µm (10~20 µm for organic substrates); die-to-die communication bandwidth reaches the TB/s scale.
• The H100 uses CoWoS-S, placing the GPU die and 6 HBM3 stacks on a silicon interposer of ~2,500 mm²; the B200 uses 5th-generation CoWoS-L, with an interposer of ~5,000 mm² (~7% of a 12-inch wafer surface area).
• Global CoWoS capacity demand: ~300K wafers/month in 2024 → over 800K wafers/month in 2026, a CAGR of over 60% (Yole Intelligence).
• HBM3: 12-Hi, 24 GB/stack, 819 GB/s (NVIDIA H100: 80 GB HBM3 / 5 stacks / 3.35 TB/s; AMD MI300X: 192 GB HBM3 / 8 stacks).
• HBM3E: over 1.2 TB/s per stack (Samsung's official 12-layer figure is 1,180 GB/s @ 9.2 Gbps; SK hynix 12-layer entered mass production in 2024-09 @ 9.6 Gbps).
• HBM4: JEDEC JESD270-4 (2025-04-16) sets 2048-bit / 32 channels / up to ~2 TB/s.
• Blackwell HGX B200: 8 GPUs with up to 1.4 TB HBM3E; the GB200 NVL72 rack: 72 GPUs totaling 13.4 TB HBM3E / 576 TB/s (NVIDIA official website, Level A).
• Market concentration: SK hynix ~50%, Samsung ~30%, Micron ~20%.

3.2. AMD EPYC and Intel Ponte Vecchio: Chiplet Architecture Benchmarks

Evidence level: B (ai-mst.com); some figures Level C

3.2.1. Background

A monolithic SoC is constrained by reticle size and cannot grow in area indefinitely; at the same time, different functional modules have different process-node requirements (compute cores need advanced nodes, while I/O and analog modules do not). The Chiplet architecture splits a monolithic die into multiple bare dies, each choosing the most suitable process node, then integrating them via advanced packaging.

3.2.2. Approach

• AMD 4th-generation EPYC (Genoa): up to 12 5nm CCD chiplets + a single 6nm IOD, integrated via packaging interconnects into a complete server processor.
• Intel Ponte Vecchio GPU: integrates 40+ chiplets across different process nodes in a single package, using a packaging scheme combining EMIB (embedded multi-die interconnect bridge) and Foveros.

3.2.3. Results

• AMD EPYC Genoa has been steadily gaining server-market share thanks to its chiplet architecture.
• Intel Ponte Vecchio demonstrates the scale limit of heterogeneous integration within a single package: 40+ chiplets across multiple process nodes.
• The Intel Data Center GPU Max series is built with EMIB 3.5D technology; some sources describe it as a production chip with 47 active modules, 5 process nodes, and over 100 billion transistors (Level C).

Engineering significance: the chiplet architecture transforms "designing one big chip" into "designing a chip system," shifting system-design complexity from within the die to between dies — this is precisely where the packaging direction's demand on Harness is strongest: it needs to uniformly manage the metadata, interconnect configuration, test access, and sign-off state of multiple bare dies.

3.3. Synopsys Acquires Ansys: Bridging EDA and Multiphysics Simulation

Evidence level: A (Synopsys official press release / Technology Magazine)

3.3.1. Background

Under multi-chip architectures, designers must simulate and analyze the interaction of thermal, power, and signal integrity among multiple dies within a single package to ensure performance and reliability. Traditionally, EDA and system-level simulation belonged to two separate worlds: EDA tools handle electrical and physical implementation, while system simulation tools handle thermal, fluid, and structural mechanics. The two do not share data, and iteration is fragmented.

3.3.2. Approach

A USD 35 billion acquisition, announced on 2024-01-16 and completed on 2025-07-17.

• Consideration structure: Ansys shareholders receive USD 197.00 cash per share + 0.3450 shares of Synopsys common stock (amounting to ~USD 35 billion at the 2023-12-21 closing price of USD 559.96); the USD 19 billion cash consideration is financed through cash + a USD 16 billion committed debt facility.
• Regulatory path: EU Phase 1 approval in 2025-01; the US HSR waiting period expired; China's SAMR granted conditional approval on 2025-07-14, requiring Synopsys to divest its entire optical and photonic device simulation business, Ansys to divest its power-analysis software business, plus 10-year behavioral remedies (may not refuse customer renewals or engage in bundling/tying).
• Technology plans: after the merger, the TAM expands from ~USD 19 billion in EDA to ~USD 31 billion in "silicon-to-system" engineering solutions; first integrated capabilities to launch in H1 2026, focused on multiphysics simulation across the EDA stack, with emphasis on multi-die advanced packaging; typical applications include integrating Ansys RedHawk-SC (power integrity) with Synopsys Fusion Compiler to identify and mitigate thermal hotspots and mechanical stress early in design.
• Financial targets: an expected USD 400 million in cost synergies in year 3 + USD 400 million in revenue synergies in year 4.

3.3.3. Results

The significance of this transaction lies not in short-term financial numbers but in the fact that it validates the judgment that "thermal-mechanical-electrical co-simulation is the core engineering problem of advanced packaging." The planned RedHawk-SC and Fusion Compiler integration moves power-integrity analysis earlier in design, avoiding costly late-stage rework — this is exactly what Harness's L5 evaluation layer should do: move the evaluator earlier to shorten the feedback loop.

Implications for the packaging-direction Harness: once multiphysics simulation and design implementation are connected, the packaging-direction Harness gains the conditions for a complete "design-simulation-sign-off" closed loop. Until then, multiphysics iteration in the packaging direction relies heavily on manual data handling, making the L1 Context Engineering layer bottleneck especially prominent.

4. Practice Standards

Nature statement: the AGENTS.md and SKILL.md below are proposed drafts distilled from publicly available industry practices, and are not official industry-standard originals. As of the writing of this document, no public AGENTS.md or SKILL.md standard template targeting the packaging direction has been found.

4.1. AGENTS.md Specification

4.1.1. AGENTS.md (Packaging Direction)

# AGENTS.md —— 封装

> 本文为基于行业实践提炼的建议稿，非官方行业标准原文。

## 角色与边界
- 角色：封装设计智能体，负责 Chiplet 互连配置、信号与电源完整性、热与应力协同、
  可测性架构生成与封装签核辅助。
- 编排仿真器，不替代仿真器：所有 SI/PI、热、应力结论必须由真实仿真工具给出。
- 不负责：封装平台选型的最终商务决策、封装厂工艺选择、封装签核放行签字。
- 多厂商协作场景须明确各 chiplet 的 IP 归属与数据可见范围。

## 环境假设
执行前必须显式声明：
- 封装平台类型：CoWoS-S / CoWoS-L / CoWoS-R、SoIC、EMIB、Foveros、I-Cube / X-Cube。
- 键合方式：微凸块 / 混合键合；以及对应精度要求（传统 ±10~25 µm，混合键合亚微米级）。
- 互连标准版本：UCIe 1.1 / 2.0 / 3.0，以及所选 profile（UCIe-S 或 UCIe-A）。
- IP 元数据格式：IEEE 1685-2022 IP-XACT。
- 存储接口标准：JESD235 / JESD238 / JESD270-4（HBM 世代与堆叠层数）。
- 3D 堆叠测试访问架构：IEEE Std 1838-2019；DFT 标准族 IEEE 1149.1 / 1149.6 / 1500 / 1687。
- 仿真工具及版本：3DIC Compiler / RedHawk-SC / Icepak / Ansys 多物理场 / 芯和半导体平台。
- 热特性表征标准：JESD51 系列。
- 未声明封装平台与互连标准版本时，禁止产出与带宽、热、应力相关的任何结论。

## 上下文加载顺序（Context Budget）
1. 系统架构定义与 chiplet 划分、互连拓扑。
2. 各 chiplet 的 IP-XACT 元数据（IEEE 1685-2022）与 bump map 定义。
3. UCIe 配置参数与一致性要求。
4. 多物理场模型与工艺设计包（基板叠层、材料参数、热边界条件）。
5. 历史封装设计的良率与可靠性数据。
- 完整版图、三维温度场、应力云图不进上下文，以路径引用 + 工具查询代替。

## 工具契约
- 优先为 SI/PI/热/应力仿真器封装 MCP 服务器，通过标准化接口调用。
- 工具返回值必须包含：退出码、日志路径、关键指标数值、工具版本、网格或精度设置。
- 多物理场迭代须声明收敛判据与最大迭代轮次。
- 跨工具数据交换须记录坐标系、单位与精度约定，禁止隐式换算。
- 不可逆工具（封装签核放行、版图投片）默认不授予直接调用权限。

## 任务执行流程（SOP）
- S1 需求解析：把封装设计目标分解为带宽、热、应力、成本的可判定子目标。
- S2 基线建立：建立基线多物理场仿真，记录温度、IR drop、应力、带宽。
- S3 候选生成：产出候选互连配置、叠层方案、材料方案，每个附理由与预期影响。
- S4 仿真判定：调用 SI/PI/热/应力仿真器，得到客观数值。
- S5 协同优化：按 STCO 方法学做多轮迭代，记录每轮收敛情况。
- S6 签核校验：执行 DRC/LVS 与热-力-电签核。
- S7 证据打包：命令、脚本、日志路径、数值、工具版本齐备。
- S8 人工确认：封装平台选型与签核放行进入人工审批队列。

## 验证与证据要求
- 互连配置合法性须依据 UCIe 规范校验：数据率、通道长度、侧带速率、bump map 列数
  必须落在所选版本的允许范围内。
- UCIe PHY 仿真验证须覆盖：电压传递函数（VTF）合规、系统误码率（BER）、
  眼图参数（高度、宽度、偏斜、掩膜余量）、前向时钟的异步行为分析。
- 热与应力结论须来自仿真，禁止用经验值或类比替代。
- 3D 堆叠须验证 IEEE 1838 测试访问架构可用性：主/从 TAP、Die Wrapper Register（DWR）、
  Flexible Parallel Port（FPP）。
- 每条结论须附：工具名 + 版本 + 命令或脚本 + 日志路径 + 关键数值 + 精度设置。

## 失败与升级策略
- 多物理场迭代在最大轮次内不收敛 → 升级人工，输出残差与不收敛维度分析。
- 出现跨域冲突（如热改善但应力恶化）→ 升级人工做权衡决策，不得自行取舍。
- UCIe 一致性检查不通过 → 停止，输出违规项与规范条款对照。
- KGD 策略缺失或不明确 → 停止堆叠方案设计，先补齐 KGD 测试方案。
- 升级时须交付：已完成证据包 + 失败点定位 + 下一步可执行的具体命令。

## 安全与合规红线
- 多厂商 chiplet 场景中，各厂商 IP 的可见范围须严格遵守授权约定；
  不得把 A 厂商 chiplet 内部结构暴露给 B 厂商的上下文。
- 自主智能体必须在沙箱运行时内执行。
- 封装版图、叠层结构、材料配方属企业核心资产，不得离开企业网络边界。
- 第三方 IP 按 IEEE 1735-2023 做加密与权限管理。
- 车规场景须符合 ISO 26262-11:2018；宽温域与抗振动要求须明确声明。
- 所有工具调用与人工确认写入不可篡改审计日志。

## 禁止事项
- 禁止编造或臆测带宽、温度、应力、IR drop、误码率数值。
- 禁止输出"应该没问题""大概率满足"等不可判定表述。
- 禁止在未声明封装平台与互连标准版本的前提下给出性能结论。
- 禁止跨厂商泄露 chiplet 内部结构。
- 禁止放宽签核规则或忽略 DRC/LVS 违规项。
- 禁止虚构标准编号；未确认标准一律标注 [待核实]。
- 禁止在无人确认下触发封装签核放行与版图投片。
- 禁止引用来源不明的协议市场份额数字。

## 输出格式
- 首行给出可判定结论（通过 / 不通过 / 部分通过 + 阻塞项）。
- 证据表：工具、版本、命令或脚本、日志路径、关键数值、精度设置、与基线差值。
- 多物理场分项：SI、PI、热、应力分别列出，并标注是否满足签核阈值。
- 标准合规表：UCIe 版本与配置项、IEEE 1838 架构项、JEDEC 存储接口项的逐条对照。
- 风险与假设：列出结论依赖的边界条件（环境温度、功耗剖面、材料参数来源）。
- 待人工确认项：平台选型、跨域权衡、签核放行。
- 数值规范：参数带单位；范围用 ~ 连接；温度用 ℃；百分比数值与 % 之间不留空格。

## 评估与自检
- 本轮所有数值是否来自真实仿真输出？
- 封装平台与互连标准版本是否已在环境假设中声明？
- UCIe 配置是否逐条对照规范校验？
- SI、PI、热、应力是否分别报告？是否存在只报有利维度的情况？
- 跨域冲突是否已升级人工而非自行取舍？
- KGD 测试方案是否已覆盖？
- 是否存在跨厂商 IP 越界暴露？
- 输出中是否残留 XX、___ 等非标准占位符？
- Harness 或提示词变更后，是否在固定黄金案例集上回归并报告与上一版本的差值？

4.2. SKILL.md Specification

4.2.1. SKILL.md (Packaging · Chiplet Interconnect Configuration and Thermal-Mechanical-Electrical Co-optimization)

---
name: packaging-chiplet-and-multiphysics
description: 封装方向的 Chiplet 互连配置与热-力-电协同技能。当需要校验 UCIe 互连配置、
  做信号与电源完整性分析、进行热与应力协同优化、验证 IEEE 1838 测试访问架构，
  并要求多物理场结果满足签核阈值时使用。
version: 1.0
created: 2026-09-12
---

# 封装 · Chiplet 互连配置与热-力-电协同

> 本文为基于行业实践提炼的建议稿，非官方行业标准原文。

## 适用场景
- Chiplet 互连方案配置与 UCIe 规范合规校验。
- 多 die 互连的信号完整性仿真（VTF、BER、眼图）与合规判定。
- 电源完整性分析与早期热点识别。
- 热-力-电协同优化（STCO 流程）。
- 3D 堆叠的测试访问架构（IEEE 1838）设计与 KGD 策略制定。
- 玻璃基板、面板级封装等新工艺路线的可行性评估。

## 前置条件
- 已声明封装平台、键合方式、互连标准版本、IP 元数据格式。
- 已声明仿真工具及版本，且各工具的数据格式与坐标系约定明确。
- 存在基线多物理场仿真结果（温度、IR drop、应力、带宽）。
- 各 chiplet 的 IP-XACT 元数据齐备，bump map 已定义。
- 智能体运行于隔离运行时，跨厂商数据可见范围已配置。
- 具备判定器：DRC/LVS、UCIe 一致性测试、签核阈值比对。

## 输入
| 输入项 | 说明 | 必需 |
|---|---|---|
| 系统架构定义 | chiplet 划分、互连拓扑、带宽需求 | 是 |
| IP-XACT 元数据 | 各 chiplet 的接口、bump map、电气参数 | 是 |
| 封装平台参数 | 中介层类型、叠层结构、材料参数 | 是 |
| 互连标准配置 | UCIe 版本、数据率、通道长度、侧带速率 | 是 |
| 基线仿真结果 | 温度、IR drop、应力、带宽 | 是 |
| 签核阈值 | 各项指标的可接受范围 | 是 |
| 功耗剖面 | 各 chiplet 的功耗分布与工作场景 | 是 |

## 输出
| 输出项 | 说明 | 必需 |
|---|---|---|
| 可判定结论 | 通过 / 不通过 / 部分通过 + 阻塞项 | 是 |
| 标准合规表 | UCIe、IEEE 1838、JEDEC 接口项逐条对照 | 是 |
| 多物理场分项表 | SI、PI、热、应力分别列出，含与基线差值 | 是 |
| 签核状态 | DRC/LVS 与热-力-电签核结果 | 是 |
| 跨域冲突清单 | 改善一维导致另一维恶化的冲突项 | 是 |
| 证据表 | 工具、版本、命令或脚本、日志路径、数值、精度设置 | 是 |
| 待人工确认项 | 平台选型、跨域权衡、签核放行 | 是 |

## 执行步骤
1. 环境校验：核对封装平台、键合方式、互连标准版本、工具版本；缺失即停止。
2. 基线仿真：建立或重跑基线多物理场仿真，记录温度、IR drop、应力、带宽。
3. 配置校验：逐条对照 UCIe 规范校验互连配置合法性。
4. 候选生成：产出候选互连配置、叠层方案、材料方案，每个附理由与预期影响。
5. 仿真判定：调用 SI/PI/热/应力仿真器，记录命令、退出码、日志路径、精度设置。
6. 协同优化：按 STCO 方法学多轮迭代，记录每轮收敛情况与残差。
7. 冲突识别：识别跨域冲突（如热改善但应力恶化），形成冲突清单。
8. 测试架构验证：验证 IEEE 1838 测试访问架构与 KGD 策略。
9. 签核校验：执行 DRC/LVS 与热-力-电签核。
10. 证据打包与交付：列出待人工确认项，写入审计日志。

## 质量标准（DoD）
- 所有数值来自真实仿真输出，且 SI、PI、热、应力分别报告。
- UCIe 配置逐条对照规范校验，无越界项。
- UCIe PHY 仿真覆盖 VTF 合规、系统 BER、眼图参数、前向时钟异步行为。
- IEEE 1838 测试访问架构（主/从 TAP、DWR、FPP）已验证可用。
- KGD 测试策略已覆盖：堆叠前 pre-bond、中间键合、堆叠后 post-bond、封装成品最终测试。
- 跨域冲突已识别并升级人工，未自行取舍。
- 每条结论附工具名 + 版本 + 命令或脚本 + 日志路径 + 关键数值 + 精度设置。
- 输出中无 XX、___ 等非标准占位符；未确定项统一标注 [待填写] 或 [待核实]。
- 参考阈值：UCIe 3.0 数据率为 48 GT/s 与 64 GT/s（UCIe-S / UCIe-A），
  侧带通道延伸至 100 mm，完全向后兼容（级别 A）；
  CoWoS 硅中介层布线间距 0.4 µm（有机基板 10~20 µm，级别 B）；
  传统封装键合精度 ±10~25 µm，混合键合进入亚微米级（级别 B）。

## 常见失败与处理
| 失败模式 | 现象 | 处理 |
|---|---|---|
| 配置越界 | UCIe 数据率或通道长度超出规范允许范围 | 停止并输出违规项与规范条款对照 |
| 跨域冲突 | 改善一维导致另一维恶化 | 形成冲突清单，升级人工权衡，禁止自行取舍 |
| 迭代不收敛 | 多物理场迭代在最大轮次内残差不降 | 升级人工，输出残差与不收敛维度分析 |
| 数据格式错位 | 跨工具坐标系或单位不一致 | 停止，先统一约定再继续，禁止隐式换算 |
| 空证明式合规 | 一致性测试通过但覆盖不完整 | 逐项列出已覆盖与未覆盖的测试项 |
| KGD 缺失 | 堆叠方案未考虑 pre-bond 测试可达性 | 停止，先补齐 KGD 测试方案 |
| 跨厂商越界 | chiplet 内部结构暴露给非授权方 | 立即隔离上下文，上报并记录 |
| 材料参数缺失 | 热仿真缺少关键材料参数 | 标注为 [待填写]，禁止用类比值替代 |

## 示例
任务：为某 2.5D Chiplet 系统配置 UCIe 互连并完成热-力-电协同仿真。
1. 环境校验：确认封装平台为 CoWoS-S、UCIe 版本为 3.0、仿真工具版本与坐标系约定。
2. 基线仿真：记录基线结温、IR drop、翘曲、die-to-die 带宽。
3. 配置校验：对照 UCIe 3.0 校验数据率（48/64 GT/s 可选）、通道长度、
   侧带速率与 bump map 列数，确认无越界项。
4. 候选生成：产出 3 组叠层与材料方案。
5. 仿真判定：分别对 3 组方案做 SI/PI/热/应力仿真。
6. 协同优化：按 STCO 迭代 4 轮，记录每轮残差。
7. 冲突识别：方案 B 结温降低 6℃ 但翘曲增加，形成跨域冲突清单。
8. 测试架构验证：确认主/从 TAP、DWR、FPP 可用，KGD 策略覆盖四阶段。
9. 签核校验：DRC/LVS 通过，热与应力满足阈值。
10. 交付：结论"部分通过，遗留 1 个阻塞项（方案 B 的翘曲权衡需人工决策）"；
    证据表含工具版本、命令、日志路径、数值、精度设置、与基线差值。

## 关联
- 与测试方向的耦合：Chiplet 必须先 KGD 才能堆叠；UCIe 2.0 的 UDA 把测试、遥测、
  调试内置进每个 chiplet，覆盖从 sort 到现场管理的全生命周期。
- 与设计方向的耦合：Synopsys 完成收购 Ansys 后，PPA 目标将从 die 级延伸到封装级。
- 与 AI Infra 的耦合：HBM 与 CoWoS 是 AI 加速器的物理瓶颈，
  GB200 NVL72 的 13.4 TB HBM3E 直接决定可承载的模型规模。

4.3. Implementation Checklist

5. Summary

The packaging direction is the one where the L1 Context Engineering layer bottleneck is most prominent in AI Harness's six-layer model. The heterogeneous data across multiphysics, multiple vendors, and multiple standards is hard to express uniformly, making "feeding the correct context to the model" itself the main engineering challenge. The existence of UCIe (with IEEE 1685-2022 IP-XACT as the metadata foundation) and the JEDEC HBM series of standards provides an anchor for this challenge: use the metadata defined by standards as the context exchange format, rather than relying on each tool's private format.

Three judgments worth emphasizing:

1. Standards evolution has already embedded observability. UCIe 2.0's UDA builds test, telemetry, and debug capabilities into each chiplet, covering the full lifecycle from sort to field management. This means a packaging-system Harness does not need to build an observation layer from scratch — the standard already provides the interface.
2. Thermal-mechanical-electrical co-optimization is the core engineering problem of advanced packaging. Synopsys's USD 35 billion acquisition of Ansys, with its first integrated capabilities focused on multi-die advanced packaging, is industry-level evidence for this judgment. Only when multiphysics simulation and design implementation are connected does the packaging direction gain a complete "design-simulation-sign-off" loop.
3. Chiplet shifts complexity from within the die to between dies. This requires Harness to have a unified management view across bare dies: interconnect configuration, test access, and sign-off state must be orchestrated as a whole.

At the same time, an industry reality must be pointed out: Die-to-Die interconnect suffers from a protocol jungle problem — multiple Die-to-Die interconnect protocols exist globally (UCIe, TSMC LIPINCON, AMD Infinity Fabric, BoW, ACC 1.0, Chiplet Interconnect Protocol, etc.), creating ecosystem fragmentation (this statement is Level C). Market-share figures for the various protocols mostly originate from self-media and must not be cited.

Information Gap Statement

The following items have not been confirmed by Level A or Level B sources and are marked [To be verified] in the text above:

1. More than 15 Die-to-Die interconnect protocols exist globally, along with each protocol's market share (e.g., "UCIe holds 38%") — the share figures come from self-media, and this document does not cite them.
2. UCIe 1.1's covered temperature range (some sources say 0°C~125°C, while automotive customers need -40°C~150°C) has not been officially confirmed.
3. NVIDIA accounts for ~63% of CoWoS demand (Level C).
4. Intel Data Center GPU Max series' 47 active modules, 5 process nodes, and over 100 billion transistors (Level C).
5. China's advanced packaging market size of RMB 113.7 billion, domestic localization rate rising from 15% in 2023 to 28%, JCET XDFOI cost about 60% with a 4nm yield of 98.5% and advanced packaging revenue of RMB 27 billion, and Tongfu Microelectronics handling over 80% of global CPU/GPU/AI chip packaging-and-test orders (Level C, all [To be verified]).
6. The wide temperature range (-40°C~175°C), vibration resistance (20G acceleration), and other 23 automotive-grade metrics defined in the China Chiplet Industry Alliance (CCLL) Automotive Electronic Chiplet Interface White Paper; VeriSilicon's ACC 1.0 standard solution (22nm + 2D packaging, cost USD 12/unit, bandwidth limit 32 GB/s); TSMC's 3DFabric Alliance with 237 member companies (Level C, all [To be verified]).
7. 3nm design cost exceeding USD 600 million, monolithic SoC area limit of ~800 mm², and ~30% yield for an 800 mm² large chip versus 70%~80% yield for 4×200 mm² chiplets (Level C).
8. The numbers and issuing organizations of China's advanced packaging-related standards (ACC 1.0, CCLL white paper) have not been officially confirmed.
9. The specific current editions of IEEE 1149.1, IEEE 1149.6, IEEE 1500, and IEEE 1687 have not been confirmed on the IEEE website; this document only lists standard names and confirmed publication years.
10. No public AGENTS.md or SKILL.md standard template targeting the packaging direction has been found; this document is a proposed draft.

6. References

1. UCIe 3.0 Specification (released 2025-08-05) — UCIe Consortium. https://www.uciexpress.org/post/ucie-at-the-future-of-memory-and-storage-2025
2. UCIe Specifications — UCIe Consortium. https://www.uciexpress.org/specifications
3. UCIe Webinars (UCIe 2.0 technical briefing) — UCIe Consortium. https://www.uciexpress.org/webinars
4. UCIe and Chiplet interconnect survey — ACM Computing Surveys. https://dl.acm.org/doi/10.1145/3819235
5. Advanced Packaging, Chiplet, CoWoS and HBM deep analysis — ai-mst.com. https://ai-mst.com/insight/en-advanced-packaging-chiplet-cowos-hbm/
6. High Bandwidth Memory (HBM) technical page — Electronics Guide. https://www.electronicsguide.net/foundations-and-theory/signal-integrity/memory-system-signal-integrity/high-bandwidth-memory
7. HBM DRAM and AI Memory Demand (citing JEDEC / Samsung / SK hynix official sources) — IntuitionLabs. https://intuitionlabs.ai/articles/hbm-dram-ai-memory-demand
8. Accellera Standards — IP-XACT (IEEE 1685-2022) — Accellera. https://www.accellera.org/downloads/standards/ip-xact
9. Synopsys Completes Acquisition of Ansys (2025-07-17) — Synopsys. https://www.synopsys.com/ja-jp/japan/press-releases/2025-07-17.html
10. How Synopsys' $35bn Ansys Deal Reshapes Engineering Software — Technology Magazine. https://technologymagazine.com/news/how-synopsys-35bn-ansys-deal-reshapes-engineering-software
11. SEMI China · HIIC 2025 Advanced Packaging Forum official minutes — SEMI China. https://www.semi.org.cn/site/semi/article/522383c3564542f68f22bca20d0b6a43.html
12. IEEE 1838 Explained: How DFT Evolves for 2.5D, 3D and 3.5D ICs — LoveChip. https://www.lovechip.com/blog/ieee-1838-explained-how-dft-evolves-for-2-5d-3d-and-3-5d-ics
13. Key points of UCIe PHY simulation and verification (citing Keysight) — EE World Online. https://www.eeworldonline.com/?p=511270
14. Chinese Journal of Electronics (English edition) · Survey of 3D stacking testing (CJE 2025). https://cje.ejournal.org.cn/article/doi/10.23919/cje.2025.00.160
15. NVIDIA GB200 NVL72 — NVIDIA official website. https://www.nvidia.com/en-us/data-center/gb200-nvl72/